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2010 – 2019
- 2015
[j2]Go Matsukawa, Yohei Nakata, Yasuo Sugure, Shigeru Oho, Yuta Kimi, Masafumi Shimozawa, Shuhei Yoshida, Hiroshi Kawaguchi
, Masahiko Yoshimoto:
A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme. IEICE Trans. Electron. 98-C(4): 333-339 (2015)- 2014
- [c2]Go Matsukawa, Yohei Nakata, Yuta Kimi, Yasuo Sugure, Masafumi Shimozawa, Shigeru Oho, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM. ARCS Workshops 2014: 1-5 - 2011
- [c1]Yohei Nakata, Yasuhiro Ito, Yasuo Sugure, Shigeru Oho, Yusuke Takeuchi, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Model-based fault injection for failure effect analysis - Evaluation of dependable SRAM for vehicle control units. DSN Workshops 2011: 91-96
2000 – 2009
- 2006
- [j1]Yasuo Sugure, Seiji Takeuchi, Yuichi Abe, Hiromichi Yamada, Kazuya Hirayanagi, Akihiko Tomita, Kesami Hagiwara, Takeshi Kataoka, Takanori Shimura:
Low-Latency Superscalar and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications. IEICE Trans. Electron. 89-C(6): 844-850 (2006)
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