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2020 – today
- 2020
[j84]Kento Watanabe
, Shintaro Izumi, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Heartbeat Interval Error Compensation Method for Low Sampling Rates Photoplethysmography Sensors. IEICE Trans. Commun. 103-B(6): 645-652 (2020)- [j83]Reiya Kawamoto, Masakazu Taichi, Masaya Kabuto, Daisuke Watanabe, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Go Matsukawa, Toshio Goto, Motoshi Kojima:
A 1.15-TOPS 6.57-TOPS/W Neural Network Processor for Multi-Scale Object Detection With Reduced Convolutional Operations. IEEE J. Sel. Top. Signal Process. 14(4): 634-645 (2020) - [c112]Reiya Kawamoto, Masakazu Taichi, Masaya Kabuto, Daisuke Watanabe, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
A 1.15-TOPS 6.57-TOPS/W DNN Processor for Multi-Scale Object Detection. AICAS 2020: 203-207 - [c111]Daisuke Watanabe, Yuji Yano, Shintaro Izumi, Hiroshi Kawaguchi, Kiyoshi Takeuchi, Toshiro Hiramoto, Shoichi Iwai, Masami Murakata, Masahiko Yoshimoto:
An Architectural Study for Inference Coprocessor Core at the Edge in IoT Sensing. AICAS 2020: 305-309
2010 – 2019
- 2019
- [j82]Masahiko Yoshimoto, Shintaro Izumi:
Recent Progress of Biomedical Processor SoC for Wearable Healthcare Application: A Review. IEICE Trans. Electron. 102-C(4): 245-259 (2019) - [j81]Shintaro Izumi, Takaaki Okano, Daichi Matsunaga, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Non-Contact Instantaneous Heart Rate Extraction System Using 24-GHz Microwave Doppler Sensor. IEICE Trans. Commun. 102-B(6): 1088-1096 (2019) - [j80]Kento Watanabe, Shintaro Izumi, Kana Sasai, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Low-Noise Photoplethysmography Sensor Using Correlated Double Sampling for Heartbeat Interval Acquisition. IEEE Trans. Biomed. Circuits Syst. 13(6): 1552-1562 (2019) - [j79]Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(4): 1442-1453 (2019) - [j78]Seiya Yoshida, Shintaro Izumi, Koichi Kajihara, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Energy-Efficient Spectral Analysis Method Using Autoregressive Model-Based Approach for Internet of Things. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(10): 3896-3905 (2019) - [j77]Takaaki Okano, Shintaro Izumi, Takumi Katsuura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Multimodal Cardiovascular Information Monitor Using Piezoelectric Transducers for Wearable Healthcare. J. Signal Process. Syst. 91(9): 1053-1062 (2019) - [c110]Yuji Yano, Seiya Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Tetsuya Hirose, Masaya Miyahara, Teruki Someya, Kenichi Okada, Ippei Akita, Yoshihiko Kurui, Hideyuki Tomizawa, Masahiko Yoshimoto:
An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment. A-SSCC 2019: 267-270 - [c109]Seiya Yoshida, Shintaro Izumi, Yuki Nishikawa, Kento Watanabe, Kana Sasai, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Heartbeat Interval Error Compensation Method Using Multiple Linear Regression for Photoplethysmography Sensors. BioCAS 2019: 1-4 - [c108]Kana Sasai, Shintaro Izumi, Kento Watanabe, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Low-Power Photoplethysmography Sensor using Correlated Double Sampling and Reference Readout Circuit. IEEE SENSORS 2019: 1-4 - 2018
- [j76]Go Matsukawa, Taisuke Kodama, Yuri Nishizumi, Koichi Kajihara, Chikako Nakanishi, Shintaro Izumi, Hiroshi Kawaguchi, Toshio Goto, Takeo Kato, Masahiko Yoshimoto:
A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video [IEICE Electronics Express Vol. 14(2017) No. 15 pp. 20170668]. IEICE Electron. Express 15(12): 20188003 (2018) - [j75]Motofumi Nakanishi, Shintaro Izumi, Mio Tsukahara, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Masahiko Yoshimoto:
A 11.3-µA Physical Activity Monitoring System Using Acceleration and Heart Rate. IEICE Trans. Electron. 101-C(4): 233-242 (2018) - [c107]Tetsuya Youkawa, Haruki Mori, Yuki Miyauchi, Kazuki Yamada, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
Delayed Weight Update for Faster Convergence in Data-Parallel Deep Learning. GlobalSIP 2018: 663-667 - [c106]Haruki Mori, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep Learning. ICECS 2018: 161-164 - [c105]Yuki Miyauchi, Haruki Mori, Tetsuya Youkawa, Kazuki Yamada, Shintato Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Atsuki Inoue:
Layer Skip Learning using LARS variables for 39% Faster Conversion Time and Lower Bandwidth. ICECS 2018: 673-676 - [c104]Yuki Nishikawa, Shintaro Izumi, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Sampling Rate Reduction for Wearable Heart Rate Variability Monitoring. ISCAS 2018: 1-5 - [c103]Kazuki Yamada, Haruki Mori, Tetsuya Youkawa, Yuki Miyauchi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
Adaptive Learning Rate Adjustment with Short-Term Pre-Training in Data-Parallel Deep Learning. SiPS 2018: 100-105 - [c102]Koichi Kajihara, Shintaro Izumi, Seiya Yoshida, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Hardware Implementation of Autoregressive Model Estimation Using Burg's Method for Low-Energy Spectral Analysis. SiPS 2018: 199-204 - 2017
- [j74]Go Matsukawa, Taisuke Kodama, Yuri Nishizumi, Koichi Kajihara, Chikako Nakanishi, Shintaro Izumi, Hiroshi Kawaguchi, Toshio Goto, Takeo Kato, Masahiko Yoshimoto:
A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video. IEICE Electron. Express 14(15): 20170668 (2017) - [c101]Mio Tsukahara, Shintaro Izumi, Motofumi Nakanishi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori:
A 19-μA metabolic equivalents monitoring SoC using adaptive sampling. ASP-DAC 2017: 37-38 - [c100]Takumi Katsuura, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Shusuke Yoshimoto, Tsuyoshi Sekitani:
Wearable pulse wave velocity sensor using flexible piezoelectric film array. BioCAS 2017: 1-4 - [c99]Yuki Nagasato, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Capacitively coupled ECG sensor system with digitally assisted noise cancellation for wearable application. BioCAS 2017: 1-4 - [c98]Takaaki Okano, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Non-contact biometric identification and authentication using microwave Doppler sensor. BioCAS 2017: 1-4 - [c97]Ryota Nakamura, Shintaro Izumi, Hiroshi Kawaguchi, Hidetoshi Ohta, Masahiko Yoshimoto:
A swallowable sensing device platform with wireless power feeding and chemical reaction actuator. EMBC 2017: 3040-3043 - [c96]Haruki Mori, Tetsuya Youkawa, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Atsuki Inoue:
A layer-block-wise pipeline for memory and bandwidth reduction in distributed deep learning. MLSP 2017: 1-6 - [c95]Yuri Nishizumi, Go Matsukawa, Koichi Kajihara, Taisuke Kodama, Shintaro Izumi, Hiroshi Kawaguchi, Chikako Nakanishi, Toshio Goto, Takeo Kato, Masahiko Yoshimoto:
FPGA implementation of object recognition processor for HDTV resolution video using sparse FIND feature. SiPS 2017: 1-6 - [c94]Takaaki Okano, Shintaro Izumi, Takumi Katsuura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Multimodal cardiovascular information monitor using piezoelectric transducers for wearable healthcare. SiPS 2017: 1-6 - 2016
- [j73]Go Matsukawa, Yuta Kimi, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(6): 1198-1205 (2016) - [j72]Haruki Mori, Yohei Umeki, Shusuke Yoshimoto, Shintaro Izumi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor. IEICE Trans. Electron. 99-C(8): 901-908 (2016) - [j71]Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii:
A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM. IPSJ Trans. Syst. LSI Des. Methodol. 9: 79-83 (2016) - [c93]Yuta Kawamoto, Shintaro Izumi, Yoshito Tanaka, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Capacitively coupled ECG sensor using a single electrode with adaptive power-line noise cancellation. BHI 2016: 212-215 - [c92]Daichi Matsunaga, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Non-contact Instantaneous Heart Rate Monitoring Using Microwave Doppler Sensor and Time-Frequency Domain Analysis. BIBE 2016: 172-175 - [c91]Yoshito Tanaka, Shintaro Izumi, Yuta Kawamoto, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Adaptive noise cancellation method for capacitively coupled ECG sensor using single insulated electrode. BioCAS 2016: 296-299 - [c90]Mio Tsukahara, Motofumi Nakanishi, Shintaro Izumi, Yozaburo Nakai, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Low-power metabolic equivalents estimation algorithm using adaptive acceleration sampling. EMBC 2016: 1878-1881 - [c89]Ryota Nakamura, Shintaro Izumi, Hiroshi Kawaguchi, Hidetoshi Ohta, Masahiko Yoshimoto:
Swallowable sensing device for long-term gastrointestinal tract monitoring. EMBC 2016: 3039-3042 - [c88]Mio Tsukahara, Shintaro Izumi, Motofumi Nakanishi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori:
A 15-μA metabolic equivalents monitoring system using adaptive acceleration sampling and normally off computing. ICECS 2016: 61-64 - [c87]Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
An low-energy 8T dual-port SRAM for image processor with selective sourceline drive scheme in 28-nm FD-SOI process technology. ICECS 2016: 532-535 - [c86]Shuhei Yoshida, Go Matsukawa, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
An soft error propagation analysis considering logical masking effect on re-convergent path. IOLTS 2016: 13-16 - 2015
- [j70]Go Matsukawa, Yohei Nakata, Yasuo Sugure, Shigeru Oho, Yuta Kimi, Masafumi Shimozawa, Shuhei Yoshida, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme. IEICE Trans. Electron. 98-C(4): 333-339 (2015) - [j69]Shintaro Izumi, Masanao Nakano, Ken Yamashita, Yozaburo Nakai, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Noise Tolerant Heart Rate Extraction Algorithm Using Short-Term Autocorrelation for Wearable Healthcare Systems. IEICE Trans. Inf. Syst. 98-D(5): 1095-1103 (2015) - [j68]Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
An I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter. IEICE Trans. Electron. 98-C(6): 489-495 (2015) - [j67]Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
Low-Jitter Design for Second-Order Time-to-Digital Converter Using Frequency Shift Oscillators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1475-1481 (2015) - [j66]Keisuke Okuno, Shintaro Izumi, Kana Masaki, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Fast Settling All Digital PLL Using Temperature Compensated Oscillator Tuning Word Estimation Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2592-2599 (2015) - [j65]Shintaro Izumi, Ken Yamashita, Masanao Nakano, Shusuke Yoshimoto, Tomoki Nakagawa, Yozaburo Nakai, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto:
Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector. IEEE Trans. Biomed. Circuits Syst. 9(5): 641-651 (2015) - [j64]Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto:
A Wearable Healthcare System With a 13.7 µ A Noise Tolerant ECG Processor. IEEE Trans. Biomed. Circuits Syst. 9(5): 733-742 (2015) - [c85]Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii:
A negative-resistance sense amplifier for low-voltage operating STT-MRAM. ASP-DAC 2015: 8-9 - [c84]Yozaburo Nakai, Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 14µA ECG processor with noise tolerant heart rate extractor and FeRAM for wearable healthcare systems. ASP-DAC 2015: 16-17 - [c83]Yuta Kimi, Go Matsukawa, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent Path. ATS 2015: 139-144 - [c82]Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor. CICC 2015: 1-4 - [c81]Motofumi Nakanishi, Shintaro Izumi, Sho Nagayoshi, Hironori Sato, Hiroshi Kawaguchi, Masahiko Yoshimoto, Takafumi Ando, Satoshi Nakae, Chiyoko Usui, Tomoko Aoyama, Shigeho Tanaka:
Physical activity group classification algorithm using triaxial acceleration and heart rate. EMBC 2015: 510-513 - [c80]Taisuke Kodama, Shintaro Izumi, Kana Masaki, Hiroshi Kawaguchi, Kazusuke Maenaka, Masahiko Yoshimoto:
Large displacement haptic stimulus actuator using piezoelectric pump for wearable devices. EMBC 2015: 1172-1175 - [c79]Hidetoshi Ohta, Shintaro Izumi, Masahiko Yoshimoto:
A more acceptable endoluminal implantation for remotely monitoring ingestible sensors anchored to the stomach wall. EMBC 2015: 4089-4092 - [c78]Daichi Matsunaga, Shintaro Izumi, Keisuke Okuno, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Non-contact and noise tolerant heart rate monitoring using microwave doppler sensor and range imagery. EMBC 2015: 6118-6121 - [c77]Yuta Kimi, Go Matsukawa, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
An accurate soft error propagation analysis technique considering temporal masking disablement. IOLTS 2015: 23-25 - [c76]Tomoki Nakagawa, Shintaro Izumi, Koji Yanagida, Yuki Kitahara, Shusuke Yoshimoto, Yohei Umeki, Haruki Mori, Hiroto Kitahara, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Masahiko Yoshimoto:
A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques. ISCAS 2015: 2904-2907 - [c75]Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiromitsu Kimura, Takaaki Fuchikami, Kyoji Marumoto, Yoshikazu Fujimori:
A ferroelectric-based non-volatile flip-flop for wearable healthcare systems. NVMTS 2015: 1-4 - 2014
- [j63]Guangji He, Yuki Miyamoto, Kumpei Matsuda, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 54-mw 3×-real-time 60-kword continuous speech recognition processor VLSI. IEICE Electron. Express 11(2): 20130787 (2014) - [j62]Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation. IEICE Trans. Electron. 97-C(4): 332-341 (2014) - [j61]Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Soft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(9): 1945-1951 (2014) - [j60]Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii:
STT-MRAM Operating at 0.38V Using Negative-Resistance Sense Amplifier. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2411-2417 (2014) - [j59]Kenta Takagi, Kotaro Tanaka, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Real-time Scalable Object Detection System using Low-power HOG Accelerator VLSI. J. Signal Process. Syst. 76(3): 261-274 (2014) - [c74]Go Matsukawa, Yohei Nakata, Yuta Kimi, Yasuo Sugure, Masafumi Shimozawa, Shigeru Oho, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM. ARCS Workshops 2014: 1-5 - [c73]Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Yoshikazu Fujimori:
Normally-off technologies for healthcare appliance. ASP-DAC 2014: 17-20 - [c72]Hiromitsu Kimura, Takaaki Fuchikami, Kyoji Marumoto, Yoshikazu Fujimori, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability. A-SSCC 2014: 21-24 - [c71]Shintaro Izumi, Ken Yamashita, Masanao Nakano, Tomoki Nakagawa, Yuki Kitahara, Koji Yanagida, Shusuke Yoshimoto, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto:
A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems. BioCAS 2014: 280-283 - [c70]Yozaburo Nakai, Shintaro Izumi, Masanao Nakano, Ken Yamashita, Takahide Fujii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Noise tolerant QRS detection using template matching with short-term autocorrelation. EMBC 2014: 34-37 - [c69]Keisuke Okuno, Kana Masaki, Shintaro Izumi, Toshihiro Konishi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 2.23 ps RMS jitter 3 μs fast settling ADPLL using temperature compensation PLL controller. ICECS 2014: 68-71 - [c68]Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
An 8-bit I/O-sized ADC with second-order TDC and MOM capacitor voltage-to-time converter. ICECS 2014: 223-226 - [c67]Tomoki Nakagawa, Shintaro Izumi, Shusuke Yoshimoto, Koji Yanagida, Yuki Kitahara, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 6T-4C shadow memory using plate line and word line boosting. ISCAS 2014: 2736-2739 - [c66]Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement. ISQED 2014: 16-23 - 2013
- [j58]Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
An Opampless Second-Order MASH ΔΣ ADC with Using Gated Ring Oscillator Time-to-Digital Converter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(2): 434-442 (2013) - [j57]Masahiko Yoshimoto:
Foreword. IEICE Trans. Electron. 96-C(4): 403 (2013) - [j56]Kosuke Mizuno, Kenta Takagi, Yosuke Terachi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Sub-100 mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video. IEICE Trans. Electron. 96-C(4): 433-443 (2013) - [j55]Guangji He, Takanobu Sugahara, Yuki Miyamoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 168-mW 2.4X-Real-Time 60-kWord Continuous Speech Recognition Processor VLSI. IEICE Trans. Electron. 96-C(4): 444-453 (2013) - [j54]Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM. IEICE Trans. Electron. 96-C(4): 528-537 (2013) - [j53]Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops. IEICE Trans. Electron. 96-C(4): 546-552 (2013) - [j52]Shusuke Yoshimoto, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(7): 1579-1585 (2013) - [j51]Kosuke Mizuno, Yosuke Terachi, Kenta Takagi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
An FPGA Implementation of a HOG-based Object Detection Processor. IPSJ Trans. Syst. LSI Des. Methodol. 6: 42-51 (2013) - [c65]Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 144-mW VLSI processor for real-time 60-kWord continuous speech recognition. ASP-DAC 2013: 71-72 - [c64]Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique. ASP-DAC 2013: 77-78 - [c63]Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells. ASP-DAC 2013: 79-80 - [c62]Shintaro Izumi, Masanao Nakano, Ken Yamashita, Takahide Fujii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Low-power hardware implementation of noise tolerant heart rate extractor for a wearable monitoring system. BIBE 2013: 1-4 - [c61]Shusuke Yoshimoto, Shinji Miyano, Makoto Takamiya, Hirofumi Shinohara, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure. CICC 2013: 1-4 - [c60]Takahide Fujii, Masanao Nakano, Ken Yamashita, Toshihiro Konishi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Noise-tolerant instantaneous heart rate and R-peak detection using short-term autocorrelation for wearable healthcare systems. EMBC 2013: 7330-7333 - [c59]Shintaro Izumi, Ken Yamashita, Masanao Nakano, Toshihiro Konishi, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto:
A 14 µA ECG processor with robust heart rate monitor for a wearable healthcare system. ESSCIRC 2013: 145-148 - [c58]Kenta Takagi, Kosuke Mizuno, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A sub-100-milliwatt dual-core HOG accelerator VLSI for real-time multiple object detection. ICASSP 2013: 2533-2537 - [c57]Jinwook Jung, Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi:
Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags. ISQED 2013: 216-222 - [c56]Keisuke Okuno, Shintaro Izumi, Toshihiro Konishi, Song Dae-Woo, Masahiko Yoshimoto, Hiroshi Kawaguchi:
Temperature compensation using least mean squares for fast settling all-digital phase-locked loop. NEWCAS 2013: 1-4 - [c55]Ken Yamashita, Shintaro Izumi, Masanao Nakano, Takahide Fujii, Toshihiro Konishi, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto:
A 38 μA wearable biosignal monitoring system with near field communication. NEWCAS 2013: 1-4 - [c54]Guangji He, Yuki Miyamoto, Kumpei Matsuda, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-NM 54-MW 3×-real-time VLSI processor for 60-kWord continuous speech recognition. SiPS 2013: 147-152 - 2012
- [j50]Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy. IEICE Electron. Express 9(6): 470-476 (2012) - [j49]Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique. IEICE Electron. Express 9(12): 1023-1029 (2012) - [j48]Takashi Matsuda, Shintaro Izumi, Yasuharu Sakai, Takashi Takeuchi, Hidehiro Fujiwara, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto:
Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes. IEICE Trans. Commun. 95-B(1): 178-188 (2012) - [j47]Masahiko Yoshimoto:
Foreword. IEICE Trans. Electron. 95-C(4): 413 (2012) - [j46]Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing. IEICE Trans. Electron. 95-C(4): 523-533 (2012) - [j45]Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme. IEICE Trans. Electron. 95-C(4): 572-578 (2012) - [j44]Shunsuke Okumura, Hidehiro Fujiwara, Kosuke Yamaguchi, Shusuke Yoshimoto, Masahiko Yoshimoto, Hiroshi Kawaguchi:
A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme. IEICE Trans. Electron. 95-C(4): 579-585 (2012) - [j43]Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Koji Nii, Masahiko Yoshimoto, Hiroshi Kawaguchi:
Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(8): 1359-1365 (2012) - [j42]Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure. IEICE Trans. Electron. 95-C(10): 1675-1681 (2012) - [j41]Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2226-2233 (2012) - [j40]Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme. Inf. Media Technol. 7(2): 544-555 (2012) - [j39]Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme. IPSJ Trans. Syst. LSI Des. Methodol. 5: 32-43 (2012) - [j38]Guangji He, Takanobu Sugahara, Yuki Miyamoto, Tsuyoshi Fujinaga, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40 nm 144 mW VLSI Processor for Real-Time 60-kWord Continuous Speech Recognition. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1656-1666 (2012) - [c53]Shinpei Soda, Masahide Nakamura, Shinsuke Matsumoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Implementing Virtual Agent as an Interface for Smart Home Voice Control. APSEC 2012: 342-345 - [c52]Koji Kugata, Shinpei Soda, Yohei Nakata, Shunsuke Okumura, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
Processor Coupling Architecture for Aggressive Voltage Scaling on Multicores. ARCS Workshops 2012: 375-384 - [c51]Guangji He, Takanobu Sugahara, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 168-mW 2.4×-real-time VLSI processor for 60-kWord continuous speech recognition. CICC 2012: 1-4 - [c50]Masanao Nakano, Toshihiro Konishi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Instantaneous Heart Rate detection using short-time autocorrelation for wearable healthcare systems. EMBC 2012: 6703-6706 - [c49]Shinpei Soda, Masahide Nakamura, Shinsuke Matsumoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Handsfree Voice Interface for Home Network Service Using a Microphone Array Network. ICNC 2012: 195-200 - [c48]Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Neutron-induced soft error rate estimation for SRAM using PHITS. IOLTS 2012: 138-141 - [c47]Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
A 51-dB SNDR DCO-based TDC using two-stage second-order noise shaping. ISCAS 2012: 3170-3173 - [c46]Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. ISLPED 2012: 85-90 - [c45]Masaharu Terada, Shusuke Yoshimoto, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction. ISQED 2012: 489-492 - [c44]Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, Shusuke Yoshimoto, Yohei Nakata, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Bit error rate estimation in SRAM considering temperature fluctuation. ISQED 2012: 516-519 - [c43]Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
A 62-dB SNDR second-order gated ring oscillator TDC with two-stage dynamic D-type flipflops as a quantization noise propagator. NEWCAS 2012: 289-292 - [c42]Kosuke Mizuno, Yosuke Terachi, Kenta Takagi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Architectural Study of HOG Feature Extraction Processor for Real-Time Object Detection. SiPS 2012: 197-202 - [c41]Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
A 61-dB SNDR 700 µm2 second-order all-digital TDC with low-jitter frequency shift oscillators and dynamic flipflops. VLSIC 2012: 190-191 - 2011
- [j37]Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Tsuyoshi Fujinaga, Shintaro Izumi, Yasuo Ariki, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition. IEICE Trans. Electron. 94-C(4): 448-457 (2011) - [j36]Hiroki Noguchi, Kazuo Miura, Tsuyoshi Fujinaga, Takanobu Sugahara, Hiroshi Kawaguchi, Masahiko Yoshimoto:
VLSI Architecture of GMM Processing and Viterbi Decoder for 60, 000-Word Real-Time Continuous Speech Recognition. IEICE Trans. Electron. 94-C(4): 458-467 (2011) - [j35]Toshihiro Konishi, Shintaro Izumi, Koh Tsuruda, Hyeokjong Lee, Takashi Takeuchi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(11): 2287-2294 (2011) - [j34]Shunsuke Okumura, Yuki Kagiyama, Yohei Nakata, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto:
7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2693-2700 (2011) - [j33]Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Takashi Takeuchi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2701-2708 (2011) - [j32]Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential. Inf. Media Technol. 6(2): 296-306 (2011) - [j31]Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
Data-Intensive Sound Acquisition System with Large-scale Microphone Array. Inf. Media Technol. 6(2): 307-318 (2011) - [j30]Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential. IPSJ Trans. Syst. LSI Des. Methodol. 4: 80-90 (2011) - [j29]Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
Data-Intensive Sound Acquisition System with Large-scale Microphone Array. J. Inf. Process. 19: 129-140 (2011) - [c40]Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40 nm 144 mW VLSI processor for realtime 60 kWord continuous speech recognition. CICC 2011: 1-4 - [c39]Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy. CICC 2011: 1-4 - [c38]Yohei Nakata, Yukihiro Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers. DSD 2011: 801-804 - [c37]Yohei Nakata, Yasuhiro Ito, Yasuo Sugure, Shigeru Oho, Yusuke Takeuchi, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Model-based fault injection for failure effect analysis - Evaluation of dependable SRAM for vehicle control units. DSN Workshops 2011: 91-96 - [c36]Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10-19. ESSCIRC 2011: 527-530 - [c35]Shintaro Izumi, Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shinpei Soda, Masahiko Yoshimoto, Hiroshi Kawaguchi:
Data Aggregation Protocol for Multiple Sound Sources Acquisition with Microphone Array Network. ICCCN 2011: 1-6 - [c34]Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V. ICECS 2011: 524-527 - [c33]Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. IOLTS 2011: 151-156 - [c32]Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
A 40-nm 640-µm2 45-dB opampless all-digital second-order MASH ΔΣ ADC. ISCAS 2011: 518-521 - [c31]Hiroki Noguchi, Shunsuke Okumura, Tomoya Takagi, Koji Kugata, Masahiko Yoshimoto, Hiroshi Kawaguchi:
0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM. ISQED 2011: 219-222 - [c30]Masahiro Yoshikawa, Shunsuke Okumura, Yohei Nakata, Yuki Kagiyama, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal control. ISQED 2011: 322-325 - 2010
- [j28]Takashi Matsuda, Takashi Takeuchi, Takefumi Aonishi, Masumi Ichien, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto:
A power-variation model for sensor node and the impact against life time of wireless sensor networks. IEICE Electron. Express 7(3): 197-202 (2010) - [j27]Shintaro Izumi, Takashi Takeuchi, Takashi Matsuda, Hyeokjong Lee, Toshihiro Konishi, Koh Tsuruda, Yasuharu Sakai, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto:
A 58-µW Single-Chip Sensor Node Processor with Communication Centric Design. IEICE Trans. Electron. 93-C(3): 261-269 (2010) - [c29]Hiroki Noguchi, Junichi Tani, Yusuke Shimai, Masanori Nishino, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 34.7-mW quad-core MIQP solver processor for robot control. CICC 2010: 1-4 - [c28]Shunsuke Okumura, Shusuke Yoshimoto, Kosuke Yamaguchi, Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto:
7T SRAM enabling low-energy simultaneous block copy. CICC 2010: 1-4 - [c27]Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video. FPL 2010: 608-611 - [c26]Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
Live demonstration: Intelligent ubiquitous sensor network for sound acquisition. ISCAS 2010: 1413 - [c25]Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
Intelligent ubiquitous sensor network for sound acquisition. ISCAS 2010: 1414-1417 - [c24]Hiroki Noguchi, Junichi Tani, Yusuke Shimai, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Parallel-processing VLSI architecture for mixed integer linear programming. ISCAS 2010: 2362-2365 - [c23]Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM. ISLPED 2010: 219-224
2000 – 2009
- 2009
- [j26]Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Dependable SRAM with 7T/14T Memory Cells. IEICE Trans. Electron. 92-C(4): 423-432 (2009) - [j25]Takashi Takeuchi, Shinji Mikami, Hyeokjong Lee, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto:
A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks. IEICE Trans. Electron. 92-C(6): 815-821 (2009) - [c22]Tsuyoshi Fujinaga, Kazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Parallelized viterbi processor for 5, 000-word large-vocabulary real-time continuous speech recognition FPGA system. INTERSPEECH 2009: 1483-1486 - [c21]Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme. ISQED 2009: 659-663 - [c20]Hiroki Noguchi, Tomoya Takagi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
An ultra-low-power VAD hardware implementation for intelligent ubiquitous sensor networks. SiPS 2009: 214-219 - [c19]Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection. VLSI Design 2009: 295-300 - 2008
- [j24]Yuichiro Murachi, Yuki Fukuyama, Ryo Yamamoto, Junichi Miyakoshi, Hiroshi Kawaguchi, Hajime Ishihara, Masayuki Miyama, Yoshio Matsuda, Masahiko Yoshimoto:
A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition. IEICE Trans. Electron. 91-C(4): 457-464 (2008) - [j23]Yuichiro Murachi, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer. IEICE Trans. Electron. 91-C(4): 465-478 (2008) - [j22]Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing. IEICE Trans. Electron. 91-C(4): 543-552 (2008) - [j21]Takashi Takeuchi, Yu Otake, Masumi Ichien, Akihiro Gion, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto:
Cross-Layer Design for Low-Power Wireless Sensor Node Using Wave Clock. IEICE Trans. Commun. 91-B(11): 3480-3488 (2008) - [j20]Shintaro Izumi, Takashi Takeuchi, Takashi Matsuda, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto:
Counter-Based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks. IEICE Trans. Commun. 91-B(11): 3489-3498 (2008) - [j19]Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering. IEEE Trans. Very Large Scale Integr. Syst. 16(6): 620-627 (2008) - [c18]Kazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A low memory bandwidth Gaussian mixture model (GMM) processor for 20, 000-word real-time speech recognition FPGA system. FPT 2008: 341-344 - [c17]Kosuke Mizuno, Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto:
An H.264/AVC MP@L4.1 quarter-pel motion estimation processor VLSI for real-time MBAFF encoding. ICECS 2008: 1179-1182 - [c16]Yuichiro Murachi, Kosuke Mizuno, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding. ISCAS 2008: 848-851 - [c15]Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Quality of a Bit (QoB): A New Concept in Dependable SRAM. ISQED 2008: 98-102 - 2007
- [j18]Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes. IEICE Trans. Electron. 90-C(10): 1949-1956 (2007) - [j17]Augusto Foronda, Yuhi Higuchi, Chikara Ohta, Masahiko Yoshimoto, Yoji Okada:
Service Interval Optimization with Delay Bound Guarantee for HCCA in IEEE 802.11e WLANs. IEICE Trans. Commun. 90-B(11): 3158-3169 (2007) - [j16]Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2695-2702 (2007) - [j15]Takashi Matsuda, Masumi Ichien, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto:
Data Transmission Scheduling Based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks. IEICE Trans. Commun. 90-B(12): 3410-3418 (2007) - [c14]Kentaro Kawakami, Mitsuhiko Kuroda, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture. ASP-DAC 2007: 292-297 - [c13]Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing. ISVLSI 2007: 107-112 - [c12]Takashi Matsuda, Takafumi Aonishi, Takashi Takeuchi, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto:
Multipath Routing using Isochronous Medium Access Control with Multi Wakeup Period for Wireless Sensor Networks. ISWCS 2007: 718-721 - [c11]Yuhi Higuchi, Augusto Foronda, Chikara Ohta, Masahiko Yoshimoto, Yoji Okada:
Delay Guarantee and Service Interval Optimization for HCCA in IEEE 802.11e WLANs. WCNC 2007: 2080-2085 - 2006
- [j14]Kentaro Kawakami, Miwako Kanamori, Yasuhiro Morita, Jun Takemura, Hideo Ohira, Masayuki Miyama, Masahiko Yoshimoto:
A Feed-Forward Dynamic VDD-VBB-Frequency Management for Low Power Motion Video Compression on 90NM Risc Processor. Intell. Autom. Soft Comput. 12(3): 283-298 (2006) - [j13]Noriyuki Minegishi, Junichi Miyakoshi, Yuki Kuroda, Tadayoshi Katagiri, Yuki Fukuyama, Ryo Yamamoto, Masayuki Miyama, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto:
VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation. IEICE Trans. Electron. 89-C(3): 230-242 (2006) - [j12]Shinji Mikami, Takafumi Aonishi, Hironori Yoshino, Chikara Ohta, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Aggregation Efficiency-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks. IEICE Trans. Commun. 89-B(10): 2741-2751 (2006) - [j11]Junichi Miyakoshi, Yuichiro Murachi, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing. IEICE Trans. Electron. 89-C(11): 1629-1636 (2006) - [j10]Junichi Miyakoshi, Yuichiro Murachi, Tetsuro Matsuno, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masayuki Miyama, Masahiko Yoshimoto:
A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3623-3633 (2006) - [j9]Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Kentaro Kawakami, Junichi Miyakoshi, Shinji Mikami, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3634-3641 (2006) - [j8]Kentaro Kawakami, Jun Takemura, Mitsuhiko Kuroda, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3642-3651 (2006) - [c10]Takafumi Aonishi, Takashi Matsuda, Shinji Mikami, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto:
Impact of Aggregation Efficiency on GIT Routing forWireless Sensor Networks. ICPP Workshops 2006: 151-158 - [c9]Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. ISLPED 2006: 61-66 - [c8]Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto, Tetsuro Matsuno:
A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing. VLSI-SoC 2006: 192-197 - 2005
- [j7]Junichi Miyakoshi, Yuichiro Murachi, Koji Hamano, Tetsuro Matsuno, Masayuki Miyama, Masahiko Yoshimoto:
A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation. IEICE Trans. Electron. 88-C(4): 559-569 (2005) - [j6]Kentaro Kawakami, Miwako Kanamori, Yasuhiro Morita, Jun Takemura, Masayuki Miyama, Masahiko Yoshimoto:
Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3290-3297 (2005) - [j5]Yuichiro Murachi, Koji Hamano, Tetsuro Matsuno, Junichi Miyakoshi, Masayuki Miyama, Masahiko Yoshimoto:
A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3492-3499 (2005) - 2004
- [j4]Masayuki Miyama, Junichi Miyakoshi, Yuki Kuroda, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto:
A sub-mW MPEG-4 motion estimation processor core for mobile video application. IEEE J. Solid State Circuits 39(9): 1562-1570 (2004) - [c7]Yuki Kuroda, Junichi Miyakoshi, Masayuki Miyama, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto:
A sub-mW MPEG-4 motion estimation processor core for mobile video application. ASP-DAC 2004: 527-528 - 2003
- [j3]Hideo Ohira, Mitsuru Kodama, Masahiko Yoshimoto:
The development and impact on business of the world's first live video streaming distribution platform for 3G mobile videophone terminals. Int. J. Electron. Bus. 1(1): 94-105 (2003) - [j2]Hideo Ohira, Mitsuru Kodama, Masahiko Yoshimoto:
A world first development of a multipoint videophone system over 3G-324M protocol. Int. J. Mob. Commun. 1(3): 264-272 (2003) - [c6]Junichi Miyakoshi, Yuri Kuroda, Masayuki Miyama, Kosuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto:
A sub-mW MPEG-4 motion estimation processor core for mobile video application. CICC 2003: 181-184 - 2002
- [c5]Masayuki Miyama, Osamu Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, Junichi Miyakoshi, K. Hashimoto, Shigenobu Komatsu, M. Yagi, Masao Morimoto, Kazuo Taki, Masahiko Yoshimoto:
An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm. CICC 2002: 167-170 - 2001
- [c4]Akira Watanabe, Osamu Tooyama, Masayuki Miyama, Masahiko Yoshimoto, Junichi Akita:
An image sensor with fast extraction of objects' positions - rough vision processor. ICIP (2) 2001: 1105-1108 - 2000
- [c3]T. Kamemaru, Hideo Ohira, H. Suzuki, Ken'ichi Asano, Masahiko Yoshimoto, Tokumichi Murakami:
Media processor core architecture for realtime, bi-directional MPEG4/H.26X codec with 30 fr/s for CIF-video. CICC 2000: 473-476 - [c2]Hidenori Sato, Hideo Ohira, Masahiko Kazayama, Ayako Harada, Masahiko Yoshimoto, Okikazu Tanno, Satoshi Kumaki, Kazuya Ishibara, Atsuo Hanami, Tetsuya Mutsumura:
MPEG-2 4: 2: 2@HL encoder chip set. ISCAS 2000: 41-44
1990 – 1999
- 1995
- [j1]Kazuya Ishihara, Shinichi Masuda, Shin-ichi Hattori, Hirofumi Nishikawa, Yoshihide Ajioka, Tsuyoshi Yamada, Hiroyuki Amishiro, Shin-ichi Uramoto, Masahiko Yoshimoto, Tadashi Sumi:
A half-pel precision MPEG2 motion-estimation processor with concurrent three-vector search. IEEE J. Solid State Circuits 30(12): 1502-1509 (1995) - [c1]Hiroyuki Kawai, Yoshitugu Inoue, Robert Streitenberger, Masahiko Yoshimoto:
A highly-parallel DSP architecture for image recognition. ICASSP 1995: 3199-3202
Coauthor Index
[j84] [j83] [c112] [c111] [j82] [j81] [j80] [j79] [j78] [j77] [c110] [c109] [c108] [j76] [j75] [c107] [c106] [c104] [c103] [c102] [j74] [c101] [c100] [c99] [c98] [c97] [c96] [c95] [c94] [j73] [j72] [j71] [c93] [c92] [c91] [c90] [c89] [c88] [c87] [c86] [j69] [j68] [j67] [j66] [j65] [j64] [c85] [c84] [c83] [c82] [c81] [c80] [c79] [c78] [c77] [c76] [c75] [j63] [j60] [j59] [c73] [c72] [c71] [c70] [c69] [c68] [c67] [j58] [j56] [j55] [j53] [j51] [c65] [c62] [c60] [c59] [c58] [c56] [c55] [c54] [j48] [j38] [c53] [c52] [c51] [c50] [c49] [c48] [c47] [c44] [c43] [c42] [c41] [j37] [j35] [j33] [j31] [j29] [c40] [c35] [c32] [j27] [c29] [j20]
[j84] [j83] [c112] [c111] [j81] [j80] [j79] [j78] [j77] [c110] [c109] [c108] [j76] [j75] [c107] [c106] [c105] [c104] [c103] [c102] [j74] [c101] [c100] [c99] [c98] [c97] [c96] [c95] [c94] [j73] [j72] [j71] [c93] [c92] [c91] [c90] [c89] [c88] [c87] [c86] [j70] [j69] [j68] [j67] [j66] [j65] [j64] [c85] [c84] [c83] [c82] [c81] [c80] [c78] [c77] [c76] [c75] [j63] [j62] [j61] [j60] [j59] [c74] [c73] [c72] [c71] [c70] [c69] [c68] [c67] [c66] [j58] [j56] [j55] [j54] [j53] [j52] [j51] [c65] [c64] [c63] [c62] [c61] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [j50] [j49] [j48] [j46] [j45] [j44] [j43] [j42] [j41] [j40] [j39] [j38] [c53] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [j37] [j36] [j35] [j34] [j33] [j32] [j31] [j30] [j29] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [j28] [j27] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [j26] [j25] [c22] [c21] [c20] [c19] [j24] [j23] [j22] [j21] [j20] [j19] [c18] [c17] [c16] [c15] [j18] [j16] [j15] [c14] [c13] [c12] [j12] [j11] [j10] [j9] [j8] [c10] [c9] [c8]
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