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ORCIDAlhad Daftardar
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2020 – today
- 2024
[c4]Alhad Daftardar
, Brandon Reagen, Siddharth Garg:
SZKP: A Scalable Accelerator Architecture for Zero-Knowledge Proofs. PACT 2024: 271-283- [i2]Alhad Daftardar, Brandon Reagen, Siddharth Garg:
SZKP: A Scalable Accelerator Architecture for Zero-Knowledge Proofs. CoRR abs/2408.05890 (2024) - 2022
- [j2]Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim:
Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory. IEEE J. Solid State Circuits 57(4): 986-998 (2022) - [c3]Daniel W. Bliss, Tutu Ajayi, Ali Akoglu, Ilkin Aliyev, Toygun Basaklar, Leul Belayneh, David T. Blaauw, John S. Brunhaver, Chaitali Chakrabarti, Liangliang Chang, Kuan-Yu Chen, Ming-Hung Chen, Xing Chen, Alex R. Chiriyath, Alhad Daftardar, Ronald G. Dreslinski, Arindam Dutta, Allen-Jasmin Farcas, Y. Fu, A. Alper Goksoy, X. He, Md Sahil Hassan, Andrew Herschfelt, Jacob Holtom, Hun-Seok Kim, A. N. Krishnakumar, Y. Li, Owen Ma, Joshua Mack, Saurav Mallik, Sumit K. Mandal, Radu Marculescu, Brittany M. McCall, Trevor N. Mudge, Ümit Y. Ogras, Vishrut Pandey, Saquib Ahmad Siddiqui, Yu-Hsiu Sun, Adarsh A. Venkataramani, Xiangdong Wei, B. R. Willis, Hanguang Yu, Yufan Yue:
Enabling Software-Defined RF Convergence with a Novel Coarse-Scale Heterogeneous Processor. ISCAS 2022: 443-447 - 2021
- [c2]Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim:
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm. VLSI Circuits 2021: 1-2 - [i1]Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim:
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm. CoRR abs/2109.03024 (2021) - 2020
- [j1]Patrick Coppock, Momen K. Yacoub, Bruce L. Qin, Alhad Daftardar, Zayd Tolaymat, Vincent J. Mooney:
Hardware Root-of-Trust-based integrity for shared library function pointers in embedded systems. Microprocess. Microsystems 79: 103270 (2020)
2010 – 2019
- 2019
- [c1]Gabriela Lopez, Michael Foreman, Alhad Daftardar, Patrick Coppock, Zayd Tolaymat, Vincent J. Mooney:
Hardware Root-of-Trust Based Integrity for Shared Library Function Pointers in Embedded Systems. MECO 2019: 1-6
Coauthor Index
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