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Blair Fort
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2010 – 2019
- 2018
- [c9]Bain Syrowik, Blair Fort, Stephen Dean Brown:
Use of CPU Performance Counters for Accelerator Selection in HLS-Generated CPU-Accelerator Systems. HEART 2018: 12:1-12:6 - 2017
- [c8]Kevin Nam, Blair Fort, Stephen Dean Brown:
FISH: Linux system calls for FPGA accelerators. FPL 2017: 1-4 - 2016
- [j1]Razvan Nane
, Vlad Mihai Sima
, Christian Pilato
, Jongsok Choi, Blair Fort, Andrew Canis, Yu Ting Chen, Hsuan Hsiao, Stephen Dean Brown, Fabrizio Ferrandi
, Jason Helge Anderson, Koen Bertels:
A Survey and Evaluation of FPGA High-Level Synthesis Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1591-1604 (2016) - [p1]Andrew Canis, Jongsok Choi, Blair Fort, Bain Syrowik, Ruolong Lian, Yu Ting Chen, Hsuan Hsiao, Jeffrey B. Goeders, Stephen Dean Brown, Jason Helge Anderson:
LegUp High-Level Synthesis. FPGAs for Software Programmers 2016: 175-190 - 2014
- [c7]Blair Fort, Andrew Canis, Jongsok Choi, Nazanin Calagar, Ruolong Lian, Stefan Hadjis, Yu Ting Chen, Mathew Hall, Bain Syrowik, Tomasz S. Czajkowski, Stephen Dean Brown, Jason Helge Anderson:
Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis. EUC 2014: 120-129 - 2013
- [c6]Andrew Canis, Jongsok Choi, Blair Fort, Ruolong Lian, Qijing Huang
, Nazanin Calagar, Marcel Gort, Jia Jun Qin, Mark Aldham, Tomasz S. Czajkowski, Stephen Dean Brown, Jason Helge Anderson:
From software to accelerators with LegUp high-level synthesis. CASES 2013: 18:1-18:9 - [c5]Jiu Cheng Cai, Ruolong Lian, Mengyao Wang, Andrew Canis, Jongsok Choi, Blair Fort, Eric Hart, Emily Miao, Yanyan Zhang, Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson:
From C to Blokus Duo with LegUp high-level synthesis. FPT 2013: 486-489
2000 – 2009
- 2006
- [c4]Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown:
A Multithreaded Soft Processor for SoPC Area Reduction. FCCM 2006: 131-142 - [c3]Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow:
A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification. FPL 2006: 1-6 - 2005
- [c2]Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow:
Designing an FPGA SoC Using a Standardized IP Block Interface. FPT 2005: 341-342 - [c1]Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen Dean Brown:
Experiences with Soft-Core Processor Design. IPDPS 2005
Coauthor Index
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