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ORCIDRaminder Singh Bajwa
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2000 – 2009
- 2001
[j4]Rita Yu Chen, Mary Jane Irwin, Raminder Singh Bajwa:
Architecture-level power estimation and design experiments. ACM Trans. Design Autom. Electr. Syst. 6(1): 50-66 (2001)
1990 – 1999
- 1998
- [c13]Rita Yu Chen, Robert Michael Owens, Mary Jane Irwin, Raminder Singh Bajwa:
Validation of an Architectural Level Power Analysis Technique. DAC 1998: 242-245 - [c12]Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa:
Comparative analysis of latches and flip-flops for high-performance systems. ICCD 1998: 264-269 - [c11]Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa:
A unified approach in the analysis of latches and flip-flops for low-power systems. ISLPED 1998: 227-232 - 1997
- [j3]Raminder Singh Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Koichi Seki, Katsuro Sasaki:
Instruction buffering to reduce power in processors for signal processing. IEEE Trans. Very Large Scale Integr. Syst. 5(4): 417-424 (1997) - [c10]Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin:
Mixed-autonomy local interconnect for reconfigurable SIMD arrays. HiPC 1997: 428-431 - 1996
- [c9]Raminder Singh Bajwa, Robert Michael Owens, Thomas P. Kelliher:
Simultaneous speech segmentation and phoneme recognition using dynamic programming. ICASSP 1996: 3213-3216 - [c8]Mitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Katsuro Sasaki, Koichi Seki:
Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer. ISLPED 1996: 353-358 - 1995
- [c7]Robert Michael Owens, Raminder Singh Bajwa, Mary Jane Irwin:
Reducing the number of counters needed for integer multiplication. IEEE Symposium on Computer Arithmetic 1995: 38-41 - [c6]Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin:
The MGAP's programming environment and the *C++ language. ASAP 1995: 121-124 - 1994
- [j2]Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin:
Area Time Trade-Offs in Micro-Grain VLSI Array Architectures. IEEE Trans. Computers 43(10): 1121-1128 (1994) - [c5]Raminder Singh Bajwa, Chetana N. Keltcher, Paul Keltcher, Mary Jane Irwin:
Rapid prototyping with programmable control paths. ASAP 1994: 69-74 - [c4]Manjit Borah, Raminder Singh Bajwa, Sridhar Hannenhalli, Mary Jane Irwin:
A SIMD solution to the sequence comparison problem on the MGAP. ASAP 1994: 336-345 - 1993
- [j1]Robert Michael Owens, Thomas P. Kelliher, Mary Jane Irwin, Mohan Vishwanath, Raminder Singh Bajwa, Wen-Lin Yang:
The design and implementation of the Arithmetic Cube II, a VLSI signal processing system. IEEE Trans. Very Large Scale Integr. Syst. 1(4): 491-502 (1993) - [c3]Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin:
Image Processing with the MGAP: A Cost Effective Solution. IPPS 1993: 439-443 - [c2]Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin:
A Massively Parallel, Micro-Grained VLSI Architecture. VLSI Design 1993: 250-255 - 1992
- [c1]Robert Michael Owens, Mary Jane Irwin, Thomas P. Kelliher, Mohan Vishwanath, Raminder Singh Bajwa:
Implementing a family of high performance, micrograined architectures. ASAP 1992: 191-205
Coauthor Index
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