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Eiichi Sano
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Publications
- 2019
- [c9]Sayuri Yokoyama, Masayuki Ikebe, Yuri Kanazawa, Takahiro Ikegami, Prasoon Ambalathankandy
, Shota Hiramatsu, Eiichi Sano, Yuma Takida, Hiroaki Minamide:
A 32×32-Pixel 0.9THz Imager with Pixel-Parallel 12b VCO-Based ADC in 0.18μm CMOS. ISSCC 2019: 108-110 - 2014
- [c8]Daisuke Uchida, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano:
A 12-bit, 5.5-μW single-slope ADC using intermittent working TDC with multi-phase clock signals. ICECS 2014: 770-773 - 2013
- [c7]Toshiki Wada, Masayuki Ikebe, Eiichi Sano:
60-GHz, 9-µW wake-up receiver for short-range wireless communications. ESSCIRC 2013: 383-386 - 2012
- [c6]Kisu Kim, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano:
A 11b 5.1µW multi-slope ADC with a TDC using multi-phase clock signals. ICECS 2012: 512-515 - 2011
- [c5]Akira Kondou, Masayuki Ikebe, Junichi Motohisa, Yoshihito Amemiya, Eiichi Sano:
A 0.6-4.5 GHz inductorless CMOS low noise amplifier with gyrator-C network. ICECS 2011: 326-329 - 2010
- [c4]Muung Shin, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano:
Column parallel single-slope ADC with time to digital converter for CMOS imager. ICECS 2010: 863-866 - 2009
- [c3]Masayuki Ikebe, Daisuke Ueo, Kazuhiro Takahagi, Masaki Ohuno, Yusuke Takada, Eiichi Sano:
A 3.1-10.6 GHz RF CMOS circuits monolithically integrated with dipole antenna. ICECS 2009: 17-20 - 2007
- [j16]Yukinobu Makihara, Masayuki Ikebe, Eiichi Sano:
Evaluation of Digitally Controlled PLL by Clock-Period Comparison. IEICE Trans. Electron. 90-C(6): 1307-1310 (2007)

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