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ORCID19th ICECS 2012: Seville, Spain
- 19th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2012, Seville, Spain, December 9-12, 2012. IEEE 2012, ISBN 978-1-4673-1261-5
A1L-A Analog Circuits and Techniques I
- Aytac Atac, Christian Harder, Ralf Wunderlich, Stefan Heinen:
A low power variable GBW opamp from 60MHz to 2GHz for multi-standard receivers. 1-4 - Victoria Pisani, Ivan Grech, Owen Casha
, Edward Gatt:
Low-voltage CMOS current feedback amplifier. 5-8 - Firas Yengui, Lioua Labrak, Patrice Russo, Felipe Frantz, Nacer Abouchi:
Optimization based on surrogate modeling for analog integrated circuits. 9-12 - Ahmed Hamza, Andrew Philip, Mohamed Ali, Mohamed Dessouky, Mohamed Kassem:
Web-based analog design using tradeoff charts. 13-16 - Athanasios Dimakos, Matthias Bucher, Rupendra Kumar Sharma, Ilias Chlis:
Ultra-low voltage drain-bulk connected MOS transistors in weak and moderate inversion. 17-20
A1L-B Bioengineering Circuits and Systems I
- Christoph Bulach, Ulrich Bihr, Maurits Ortmanns:
Evaluating the influence of the bit error rate on the information of neural spike signals. 21-24 - Arsam N. Shiraz, Andreas Demosthenous, Anne Vanhoestenberghe:
Towards an optimized wearable neuromodulation device for urinary incontinence. 25-28 - Virgilio Valente, Clemens Eder, Andreas Demosthenous, Nick Donaldson:
Towards a closed-loop transmitter system with integrated class-D amplifier for coupling-insensitive powering of implants. 29-32 - Florent Dupont, Cyril Condemine, Jean-François Beche, Marc Belleville:
Multi-application electrical stimulator architecture dedicated to waveform control by electrode-tissue impedance spectra monitoring. 33-36 - Abdulnasir Hossen:
Selection of wavelet-bands for neural network discrimination of Parkinsonian tremor from essential tremor. 37-40
A1L-C Digital Signal Processing
- Alfredo Rosado, Taras Iakymchuk, Manuel Bataller, Marek Wegrzyn:
Hardware-efficient matrix inversion algorithm for complex adaptive systems. 41-44 - Taras Iakymchuk, Alfredo Rosado, Emilio Soria-Olivas, Manuel Bataller:
Implementation of a new adaptive algorithm using fuzzy cost function and robust to impulsive noise. 45-48 - Salvador Javier Haboba, Riccardo Rovatti, Gianluca Setti:
RADS converter: An approach to Analog to Information conversion. 49-52 - Lin Bai, Patrick Maechler, Michael Muehlberghuber, Hubert Kaeslin:
High-speed compressed sensing reconstruction on FPGA using OMP and AMP. 53-56
A1L-D RF Building Blocks
- Amir Hossein Masnadi Shirazi, Hooman Rashtian, Shahriar Mirabbasi:
A linearity enhancement technique and its application to CMOS wideband low-noise amplifiers. 57-60 - Tomoyuki Arai, Ali Hajimiri:
A 7GHz wideband self-correcting quadrature VCO. 61-64 - Omid Talebi Amiri, Adil Koukab:
Design methodology and integration of a 1.8GHz outphasing power amplifier for mobile terminals. 65-68 - You Zheng, Carlos E. Saavedra:
4.0-5.5 GHz tunable power splitter RFIC using active inductors. 69-72 - Wenlong Jiang, Armin Tavakol, Popong Effendrik, Marcel van de Gevel, Frank Verwaal, Robert Bogdan Staszewski:
Design of ADPLL system for WiMAX applications in 40-nm CMOS. 73-76
A1L-E SPECIAL SESSION: Computationally Intensive Applications on FPGAs
- Orsalia Georgia Hazapis, Evangelos Logaras, Elias S. Manolakos:
A soft IP core generating SoCs for the efficient stochastic simulation of large Biomolecular Networks using FPGAs. 77-80 - Konstantinos Manolopoulos, A. Belias, Georgios Georgis, Dionysios I. Reisis, E. G. Anasontzis:
Signal processing for deep-sea observatories with reconfigurable hardware. 81-84 - George Lentaris, Dionysios Diamantopoulos, G. Stamoulias, Kostas Siozios, Dimitrios Soudris, Marcos Avilés Rodrigálvarez:
FPGA-based path-planning of high mobility rover for future planetary missions. 85-88 - Ahmed Mahdi, Panagiotis Sakellariou, Nikos Kanistras, Ioannis Tsatsaragkos, Vassilis Paliouras:
Hardware design and verification techniques for Giga-bit Forward-Error Correction systems on FPGAs. 89-92 - Ioannis Vourkas, Georgios Ch. Sirakoulis:
FPGA based cellular automata for environmental modeling. 93-96 - Keishi Tsubaki, Tetsuya Hirose, Yuji Osaki, Seiichiro Shiga, Nobutaka Kuroki, Masahiro Numa:
A 6.66-kHz, 940-nW, 56ppm/°C, fully on-chip PVT variation tolerant CMOS relaxation oscillator. 97-100 - David Gascon, Andreu Sanuy, Javier J. Sieiro:
Compact class-AB follower for wideband closed loop line drivers. 101-104 - Akinori Moriyama, Satoshi Taniyama, Takao Waho:
A low-distortion switched-source-follower track-and-hold circuit. 105-108 - Damiano Cascella, Francesco Cannone, Gianfranco Avitabile, Giuseppe Coviello:
A 2.5-GS/s 62dB THD SiGe Track-and-Hold Amplifier with feedthrough cancellation technique. 109-112 - Behnam Sedighi, Anh T. Huynh, Efstratios Skafidas:
A CMOS track-and-hold circuit with beyond 30 GHz input bandwidth. 113-116
A2L-B Sensing and Sensor Networks
- Takamoto Watanabe, Hirofumi Isomura, Tomohito Terasawa:
All-Digital A/D converter TAD for sensor interface over wide temperature ranges. 117-120 - Ali Mohammadi, Mehmet R. Yuce, S. O. Reza Moheimani:
A readout circuit implementation to reduce the flicker noise in MEMS electrothermal sensors. 121-124 - Hassan Abbass, Hawraa Amhaz, Gilles Sicard, David Alleysson:
In Pixel Implementation of autoadaptative integration time. 125-128 - Jochen Rust, Steffen Paul:
Design and implementation of a neurocomputing ASIP for environmental monitoring in WSN. 129-132 - Marko Mailand, Stefan Getzlaff, Andrew David Dehennis:
A system-proof-of-concept for remote measurement applications. 133-136
A2L-C DSP Algorithm and Implementation
- Marko Butorac, Mladen Vucic:
FPGA implementation of simple digital signal processor. 137-140 - Abdallah Meraoumia, Salim Chitroub, Ahmed Bouridane:
Improving palmprint identification by combining multiple classifiers and using gabor filter. 141-144 - Gianvito Urgese, Mariagrazia Graziano, Marco Vacca, Muhammad Awais, Stefano Frache, Maurizio Zamboni:
Protein alignment HW/SW optimizations. 145-148 - Matteo Causo, Ting An, Lirida Alves de Barros Naviner:
Parallel scaling-free and area-time efficient CORDIC algorithm. 149-152 - Seyede Mahya Safavi, Mahdi Shabany:
A VLSI architecture for multiple antenna eigenvalue-based spectrum sensing. 153-156
A2L-D RF and mmWave Circuits
- Hossein Jalili, Ali Fotowat-Ahmady, Mahta Jenabi:
A 1-mW current reuse quadrature RF front-end for GPS L1 band in 0.18µm CMOS. 157-160 - Kaushik Ghosal, Tejasvi Anand, Vikram Chaturvedi, Bharadwaj Amrutur:
A power-scalable RF CMOS receiver for 2.4 GHz Wireless Sensor Network applications. 161-164 - Arash Moradi, Mohamad Sawan:
A 20 Mb/s 0.084 nJ/bit ISM-band transmitter dedicated to medical sensor networks. 165-168 - Shailesh Kulkarni, Dixian Zhao, Patrick Reynaert:
Analysis and characterization of mismatches in outphasing transmitter. 169-172 - Sophie Drean, Nicolas Martin, Nathalie Deltimple, Eric Kerherve, Baudouin Martineau, Didier Belot:
A 60GHz class F-E power VCO with vector-modulator feedback in 65nm CMOS technology. 173-176
A3L-A Analog Circuits and Techniques III
- Siraporn Sakphrom, Apinunt Thanachayanont:
A low-power CMOS RF power detector. 177-180 - Domenico Pepe, Domenico Zito:
Millimeter-wave high-Q active inductor in 65nm CMOS. 181-184 - Quentin Beraud-Sudreau, Olivier Mazouffre, Michel Pignol, Louis Baguena, Claude Neveu, Jean-Baptiste Bégueret, Thierry Taris:
Windowed phase comparator for an 80Gbit/s CDR. 185-188 - Mazyar Abedinkhan, Amir Masoud Sodagar, Reza Mohammadi, Payman Adl:
A novel multi-step C-2C DAC architecture. 189-192 - Andrea Costantini, Alessandro Pezzotta, Andrea Baschirotto, Marcello De Matteis, Stefano D'Amico, Fabrizio Murtas, Giuseppe Gorini:
A CMOS 0.13µm low power front-end for GEM detectors. 193-196
A3L-B Sensors and Photonics
- Takamoto Watanabe, Tomohito Terasawa:
All-digital A/D converter TAD for high-resolution and low-power sensor/RF interface. 197-200 - Maria-Alexandra Paun, Jean-Michel Sallese, Maher Kayal:
Temperature considerations on Hall Effect sensors current-related sensitivity behaviour. 201-204 - Juan A. Leñero-Bardallo, Wei Tang, Dongsoo Kim, Joon Hyuk Park, Eugenio Culurciello:
A tri-mode event-based vision sensor with an embedded wireless transmitter. 205-208 - Jürgen Oehm, Christian Koch, Ivan Stoychev, Andreas Gornik:
Improved high precision optical angle measurement system with no interference of light gradients and mismatch. 209-212 - Mohammed Hassan, Horst Zimmermann:
A 10Gb/s inductorless push pull current mirror transimpedance amplifier. 213-216
A3L-C Digital Circuits on FPGAs
- Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson:
Performance evaluation for FPGA-based processing of tree-like structures. 217-220 - Alexandru Amaricai, Oana Boncalo:
FPGA implementation of very high radix square root with prescaling. 221-224 - Raouf Senhadji-Navarro, Ignacio Garcia-Vargas, Jose Luis Guisado:
Performance evaluation of RAM-based implementation of Finite State Machines in FPGAs. 225-228 - Neil Scicluna, Edward Gatt, Owen Casha, Ivan Grech, Joseph Micallef:
FPGA-based autonomous parking of a car-like robot using Fuzzy Logic Control. 229-232 - Fernando Gehm Moraes, Matheus T. Moreira, Carlos Lucas, D. Correa, Douglas de O. Cardoso, M. Magnaguagno, Guilherme M. Castilhos, Ney Laert Vilar Calazans:
A generic FPGA emulation framework. 233-236
A3L-D Wireless and Wireline Communications
- Timothy De Keulenaer, Yu Ban, Zhisheng Li, Johan Bauwelinck:
Design of a 80 Gbit/s SiGe BiCMOS fully differential input buffer for serial electrical communication. 237-239 - Hazem W. Marar, Khaldoon Abugharbieh, Abdel-Karim Al-Tamimi:
A power efficient 3-Gbits/s 1.8V PMOS-based LVDS output driver. 240-243 - Anu Lehtovuori, Risto Valkonen, Martti Valtonen:
Accessible approach to wideband matching. 244-247 - Shenjie Wang, Catherine Dehollain:
A generalized graphical model to specify A/D resolution from receiver front-end. 248-251
A4L-A Analog Filters
- Raul Loeches-Sanchez, Roberto Gómez-García, Bernard Jarry, Julien Lintignat, Bruno Barelaud:
Lumped-element-based single/dual-passband analog filters using signal-interference principles. 252-255 - Antonio Jose Ginés, Alberto Villegas, Eduardo J. Peralías, Adoración Rueda:
Self-biased input common-mode generation for improving dynamic range and yield in inverter-based filters. 256-259 - Marcello De Matteis, Stefano D'Amico, Andrea Costantini, Alessandro Pezzotta, Andrea Baschirotto:
A 1.25mW 3rd-order Active-Gm-RC 250MHz-bandwidth analog filter based on power-stability optimization. 260-263 - Drazen Jurisic, Neven Mijat, George S. Moschytz:
Dynamic range improvement of new leap-frog filter using numerical optimization. 264-267 - Ginés Doménech-Asensi, F. Martinez-Viviente, J. Illade-Quinteiro, Juan Zapata-Pérez, Ramón Ruiz Merino, José-Alejandro López Alcantud, Juan Martínez-Alajarín, Francisco J. Fernández-Luque, Juan M. Carrillo, Miguel Angel Domínguez:
A fourth order CMOS band pass filter for PIR sensors. 268-271
A4L-B Mixed-signal Test and Verification
- Kamel Beznia, Ahcène Bounceur, Louay Abdallah, Ke Huang, Salvador Mir, Reinhardt Euler:
Accurate estimation of analog test metrics with extreme circuits. 272-275 - Janez Trontelj Jr., Blaz Smid, Janez Trontelj:
Single pass temperature calibration of the ASIC on a general purpose ATE. 276-279 - Leandro S. Freitas, Gabriel A. G. Andrade, Luiz C. V. dos Santos:
A template for the construction of efficient checkers with full verification guarantees. 280-283 - Laurence Pierre:
A formal framework for testing with assertion checkers in mixed-signal simulation. 284-287
A4L-C VLSI Digital Implementations
- Diogo Brito, Jorge R. Fernandes, Paulo F. Flores, José Monteiro:
Design and characterization of a QLUT in a standard CMOS process. 288-291 - Seyed Ebrahim Esmaeili, Riadul Islam, Asim J. Al-Khalili, Glenn E. R. Cowan:
Dual-edge triggered sense amplifier flip-flop utilizing an improved scheme to reduce area, power, and complexity. 292-295 - Marc Pons, Jean-Luc Nagel, Christian Piguet:
Maximum delay variation temperature-aware standard cell design. 296-299 - Ameneh Golnari, Golnoosh Sharifan, Yalda Amini, Mahdi Shabany:
A low complexity architecture for the cell search applied to the LTE systems. 300-303 - Homin Jiang, Howard Liu, Kim Guzzino, Derek Kubo, Chao-Te Li, Ray Chang:
Digitizing The Yuan Tseh Lee Array for Microwave Background Anisotropy by 5Gsps ADC boards. 304-307
A4L-D Algorithms for Communications
- Syed M. Zafi S. Shah, Abdul W. Umrani, Aftab Ahmad Memon, Syed Muhammad Zaigham Abbas Shah:
PMEPR reduction for OFCDM using SLM and PTS. 308-311 - Vivek Yenamandra, Feiran Lei, Saleh R. Al-Araji, Nazar T. Ali, Mohammed Ismail:
Adaptive slope and threshold companding technique for PAPR reduction in OFDM systems. 312-315 - Isael Diaz, Rodolfo Torrea Duran, Sofie Pollin, Liesbet Van der Perre, Viktor Öwall:
Selective channelization on an SDR platform for LTE-a carrier aggregation. 316-319 - Chinmaya Mahapatra, A. Ramakrishnan, Thanos Stouraitis, Victor C. M. Leung:
A novel implementation of sequential output based parallel processing - orthogonal wavelet division multiplexing for DAS on SDR platform. 320-323
A4L-E SPECIAL SESSION: Advances in Embedded Vision Hardware
- Stephen J. Carey, David Robert Wallace Barr, Bin Wang, Alexey Lopich, Piotr Dudek:
Mixed signal SIMD cellular processor array vision chip operating at 30, 000 fps. 324-327 - Francisco Barranco, Javier Díaz, Begoña del Pino, Eduardo Ros:
Bottom-up visual attention model based on FPGA. 328-331 - Manuel Moreno García, Óscar Guerra Vinuesa, Rocío del Río Fernández, Belén Pérez-Verdú, Ángel Rodríguez-Vázquez:
CMOS SPADs selection, modeling and characterization towards image sensors implementation. 332-335 - Jordi Albo-Canals, S. Ortega, S. Perdices, A. Badalov, Xavier Vilasís-Cardona:
Embedded low-power low-cost Camera Sensor based on FPGA and its applications in mobile robots. 336-339 - Fadoua Guezzi Messaoud, Antoine Dupret, Arnaud Peizerat, Yves Blanchard:
High Dynamic Range image sensor with self adapting integration time in 3D technology. 340-343
B1L-A Data Converters
- Marco Zamprogno, Alberto Minuti, Francesca Girardi, Germano Nicollini:
A/D conversion of the battery voltage in advanced CMOS technologies. 344-347 - Reza Mohammadi, Hossein Shamsi, Mazyar Abedinkhan:
On the design of a 2-2-0 MASH delta-sigma-pipeline modulator. 348-351 - Luis Hernández, Enrique Prefasi, Susana Patón, Pieter Rombouts:
Analysis of VCO based noise shaping ADCs linearized by PWM modulation. 352-355 - Nicolas Beilleau, Vincent P. M. Bourguet, Fernando Rangel de Sousa:
Design of an undersampled BP ΣΔ modulator using LC and time-interleaved resonators. 356-359 - Johannes Uhlig, René Schüffny:
Incremental-ΣΔ-ADCs with dynamic conversion length adaption. 360-363
B1L-B Bioengineering Circuits and Systems II
- Peter Pracný, Pere Llimos Muntal, Erik Bruun:
Interpolation filter design for hearing-aid audio class-D output stage application. 364-367 - Boram Kim, Kazuo Nakazato:
Dual data pulse width modulator for wireless Simultaneous Measurement of Redox Potential and Temperature using a Single RFID Chip. 368-371 - Dariusz Komorowski, Stanislaw Pietraszek, Damian Grzechca:
The wireless system for EGG signal acquisition. 372-375 - José L. Ausín, Javier Ramos, J. Francisco Duque-Carrillo, Guido Torelli:
A high dynamic range wideband CMOS phase angle detector for bioimpedance spectroscopy. 376-379
B1L-C SPECIAL SESSION: Digital Circuits for Embedded Control and Security
- Alberto Oliveri, Marco Storace:
Hardware-in-the-loop simulations of circuit architectures for the computation of exact and approximate explicit MPC control functions. 380-383 - Raúl Jiménez, Guillermo Feria, Juan Antonio Gómez Galán, Fernando Gómez-Bravo, Manuel Sanchez-Raya:
VLSI Implementation of digital frequency sensors as hardware countermeasure. 384-387 - Macarena C. Martínez-Rodríguez, Piedad Brox, Javier Castro-Ramirez, Erica Tena, Antonio J. Acosta, Iluminada Baturone:
ASIC-in-the-loop methodology for verification of piecewise affine controllers. 388-391 - Susana Eiroa, Javier Castro-Ramirez, Macarena Cristina Martínez-Rodríguez, Erica Tena, Piedad Brox, Iluminada Baturone:
Reducing bit flipping problems in SRAM physical unclonable functions for chip identification. 392-395
B1L-D Digital Circuits for Channel Coding
- Hazem A. Ahmed, Hamed Salah, Tallal Elshabrawy, Hossam A. H. Fahmy:
Low energy high speed reed-solomon decoder using two parallel modified evaluator Inversionless Berlekamp-Massey. 396-399 - Oscar Sanchez, C. Jegoy, Michel Jézéquel, Yannick Saouter:
High speed low complexity radix-16 Max-Log-MAP SISO decoder. 400-403 - Fabian Angarita, Vicente Torres-Carot, Asuncion Perez-Pascual, Javier Valls:
High-throughput FPGA-based emulator for structured LDPC codes. 404-407 - Vicente Torres-Carot, Asuncion Perez-Pascual, Trinidad Sansaloni, Javier Valls:
Fully-parallel LUT-based (2048, 1723) LDPC code decoder for FPGA. 408-411 - Francisco Garcia-Herrero, María José Canet, Javier Valls:
Decoder for an enhanced serial generalized bit flipping algorithm. 412-415 - Andrea Barbieri, Sergio Pernici, Germano Nicollini:
Dynamic range improvement in 2nd-order low-pass multibit ΣΔ modulators. 416-419 - Christoph Zorn, Timon Brückner, Maurits Ortmanns, Wolfgang Mathis:
Performance tuning of multi-bit continuous time ΣΔ-modulators using a switched system model. 420-423 - Sha Tao, Julian Garcia, Saul Rodriguez, Ana Rusu:
Analysis of exponentially decaying pulse shape DACs in continuous-time sigma-delta modulators. 424-427 - Matthias Lorenz, Michael Maurer, Yiannos Manoli, Maurits Ortmanns:
Joint estimation of filter nonidealities in continuous-time sigma-delta modulators by using an unscented Kalman filter. 428-431 - Timon Brückner, Martin Kiebler, Christoph Zorn, Wolfgang Mathis, Maurits Ortmanns:
Discrete-time simulation of arbitrary digital/analog converter waveforms in continuous-time sigma-delta modulators. 432-435
B2L-B Analysis and Design Techniques for Low-Power Circuits
- Majid Zamani, Clemens Eder, Andreas Demosthenous:
CBSC-based pipelined analog-to-digital converters: Power dissipation bound analysis. 436-439 - Christian Berthet, Philippe Georgelin, Janvier Ntyame, Mathieu Raffin:
Peak power estimation using activity measured on emulator. 440-443 - Mariem Slimani, Philippe Matherat, Yves Mathieu:
A dual threshold voltage technique for glitch minimization. 444-447 - S. M. Yasser Sherazi, Peter Nilsson, Henrik Sjöland, Joachim Neves Rodrigues:
A 100-fJ/cycle sub-VT decimation filter chain in 65 nm CMOS. 448-451 - Panagiotis Sakellariou, Vassilis Paliouras:
Low-power two's-complement multiplication based on selective activation. 452-455
B2L-C Circuit Level CAD
- Catalin-Adrian Tugui, R. Benassi, S. Apostol, Philippe Bénabès:
Efficient optimization methodology for CT functions based on a modified bayesian kriging approach. 456-459 - Hiroshi Tezuka, Kunihiro Fujiyoshi:
An efficient solution space for floorplan of 3D-LSI. 460-463