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2010 – 2019
- 2014
[j3]Per Hammarlund, Alberto J. Martinez, Atiq A. Bajwa, David L. Hill, Erik G. Hallnor, Hong Jiang, Martin G. Dixon, Michael Derr, Mikal Hunsaker, Rajesh Kumar, Randy B. Osborne, Ravi Rajwar, Ronak Singhal, Reynold D'Sa, Robert Chappell, Shiv Kaushik, Srinivas Chennupaty, Stéphan Jourdan, Steve Gunther, Thomas Piazza, Ted Burton:
Haswell: The Fourth-Generation Intel Core Processor. IEEE Micro 34(2): 6-20 (2014)
2000 – 2009
- 2009
- [c12]Lily Pao Looi, Stéphan Jourdan:
Transitioning the Intel® next generation microarchitectures (nehalem and westmere) into the mainstream. Hot Chips Symposium 2009: 1-18 - 2002
- [c11]Robert Cooksey, Stéphan Jourdan, Dirk Grunwald:
A stateless, content-directed data prefetching mechanism. ASPLOS 2002: 279-290 - 2001
- [j2]Pierre Michaud, André Seznec, Stéphan Jourdan:
An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors. Int. J. Parallel Program. 29(1): 35-58 (2001) - 2000
- [c10]Stéphan Jourdan, Lihu Rappoport, Yoav Almog, Mattan Erez
, Adi Yoaz, Ronny Ronen:
eXtended Block Cache. HPCA 2000: 61-70 - [c9]Michael Bekerman, Adi Yoaz, Freddy Gabbay, Stéphan Jourdan, Maxim Kalaev, Ronny Ronen:
Early load address resolution via register tracking. ISCA 2000: 306-315
1990 – 1999
- 1999
- [c8]Pierre Michaud, André Seznec, Stéphan Jourdan:
Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors. IEEE PACT 1999: 2-10 - [c7]Adi Yoaz, Mattan Erez, Ronny Ronen, Stéphan Jourdan:
Speculation Techniques for Improving Load Related Instruction Scheduling. ISCA 1999: 42-53 - [c6]Michael Bekerman, Stéphan Jourdan, Ronny Ronen, Gilad Kirshenboim, Lihu Rappoport, Adi Yoaz, Uri C. Weiser:
Correlated Load-Address Predictors. ISCA 1999: 54-63 - 1998
- [c5]Stéphan Jourdan, Ronny Ronen, Michael Bekerman, Bishara Shomar, Adi Yoaz:
A Novel Renaming Scheme to Exploit Value Temporal Locality Through Physical Register Reuse and Unification. MICRO 1998: 216-225 - 1997
- [j1]Stéphan Jourdan, Jared Stark, Tse-Hao Hsing, Yale N. Patt:
Recovery requirements of branch prediction storage structures in the presence of mispredicted-path execution. Int. J. Parallel Program. 25(5): 363-383 (1997) - 1996
- [c4]Stéphan Jourdan, Tse-Hao Hsing, Jared Stark, Yale N. Patt:
The effects of mispredicted-path execution on branch prediction structures. IEEE PACT 1996: 58-67 - [c3]André Seznec, Stéphan Jourdan, Pascal Sainrat, Pierre Michaud:
Multiple-Block Ahead Branch Predictors. ASPLOS 1996: 116-127 - 1995
- [c2]Stéphan Jourdan, Pascal Sainrat, Daniel Litaize:
Exploring Configurations of Functional Units in an Out-of-Order Superscalar Processor. ISCA 1995: 117-125 - [c1]Stéphan Jourdan, Pascal Sainrat, Daniel Litaize:
An investigation of the performance of various instruction-issue buffer topologies. MICRO 1995: 279-284
Coauthor Index
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