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ORCIDYihua Huang 0005
Person information
- affiliation: Sun Yat-Sen University, School of Electronic and Information Technology, Guangzhou, China
Other persons with the same name
- Yihua Huang — disambiguation page
- Yihua Huang 0001
![[0000-0003-1806-0936]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0003-1806-0936")
— Nanjing University, State Key Laboratory for Novel Software Technology, China - Yihua Huang 0002 — Institute of Computing Technology, Chinese Academy of Sciences, China
- Yihua Huang 0003 — China Telecom Research Institute, Guangzhou, China
- Yihua Huang 0004 — ZTE Corporation, Shenzhen, China
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2020 – today
- 2024
[j8]Yuze Peng, Shengjun Xu, Yihua Huang:
Re-HGNM: a repeat aware hypergraph neural machine for session-based recommendation. Neural Comput. Appl. 36(17): 9661-9674 (2024)- [c11]Dehao Xiang, Chenyang Li, Wenjin Huang, Yihua Huang:
A Novel FPGA Accelerator of R(2+1)D. FCCM 2024: 1-7 - [c10]Wenlu Peng, Jianjun Chen, Wenjin Huang, Yihua Huang:
MRH-GCN: An Efficient GCN Accelerator for Multi-Relation Heterogeneous Graph. FCCM 2024: 197-203 - [c9]Xiangzhi Xu, Qi Liu, Wenjin Huang, Wenlu Peng, Yihua Huang:
SpGCN: An FPGA-Based Graph Convolutional Network Accelerator for Sparse Graphs. FCCM 2024: 216 - [c8]Shengjun Xu, Wenlu Peng, Wenjin Huang, Qi Liu, Yihua Huang:
HR-GCN: An Efficient GCN Accelerator for Heterogeneous Graph Data and R-GCN Model. FPGA 2024: 186 - 2023
- [j7]Qingkun Chen, Wenjin Huang, Yihua Huang:
The Learnable Model-Based Genetic Algorithm for the IP Mapping Problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(7): 2350-2363 (2023) - [c7]Baoze Zhao, Wenjin Huang, Yihua Huang:
A Novel Hardware Accelerator of NeRF Based on Xilinx UltraScale and UltraScale+ FPGA. FPL 2023: 197-203 - [c6]Baoze Zhao, Wenjin Huang, Tianrui Li, Yihua Huang:
BSTMSM: A High-Performance FPGA-based Multi-Scalar Multiplication Hardware Accelerator. ICFPT 2023: 35-43 - 2022
- [j6]Wenjin Huang, Huangtao Wu, Qingkun Chen, Conghui Luo, Shihao Zeng, Tianrui Li, Yihua Huang:
FPGA-Based High-Throughput CNN Hardware Accelerator With High Computing Resource Utilization Ratio. IEEE Trans. Neural Networks Learn. Syst. 33(8): 4069-4083 (2022) - [c5]Shengjun Xu, Wenjin Huang, Yihua Huang:
TFR-GCN: A GCN Accelerator with Tile-Fusing Strategy. FCCM 2022: 1 - [c4]Shaofen Chen, Haiyan Lin, Wenjin Huang, Yihua Huang:
Hardware Design and Implementation of Classic McEliece Post-Quantum Cryptosystem Based on FPGA. HPEC 2022: 1-6 - [c3]Conghui Luo, Wenjin Huang, Dehao Xiang, Yihua Huang:
A High-performance Deployment Framework for Pipelined CNN Accelerators with Flexible DSE Strategy. HPEC 2022: 1-8 - [c2]Qingru Zeng, Quanxin Li, Baoze Zhao, Han Jiao, Yihua Huang:
Hardware Design and Implementation of Post-Quantum Cryptography Kyber. HPEC 2022: 1-6 - 2021
- [j5]Qingkun Chen, Wenjin Huang, Yuanshan Zhang, Yihua Huang:
An IP Core Mapping Algorithm Based on Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 189-202 (2021) - [j4]Qingkun Chen, Wenjin Huang, Yuze Peng, Yihua Huang:
A Reinforcement Learning-Based Framework for Solving the IP Mapping Problem. IEEE Trans. Very Large Scale Integr. Syst. 29(9): 1638-1651 (2021) - 2020
- [j3]Yihua Huang, Wenjin Huang, Rui Chen, Huangtao Wu, Ming Wei:
A Tag Based Random Order Vector Reduction Circuit. IEEE Access 8: 41502-41515 (2020) - [j2]Han Jiao, Xinhua Jiang, Zhiyong Pang, Xiaofeng Lin, Yihua Huang, Li Li:
Deep Convolutional Neural Networks-Based Automatic Breast Segmentation and Mass Detection in DCE-MRI. Comput. Math. Methods Medicine 2020: 2413706:1-2413706:12 (2020) - [c1]Shihao Zeng, Yihua Huang:
A Hybrid-Pipelined Architecture for FPGA-based Binary Weight DenseNet with High Performance-Efficiency. HPEC 2020: 1-5
2010 – 2019
- 2019
- [j1]Huangtao Wu, Wenjin Huang, Rui Chen, Yihua Huang:
Implementation and Area Optimization of LUT6 Based Convolution Structure on FPGA. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(12): 1813-1815 (2019)
Coauthor Index
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