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S. Sutarwala

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1990 – 1999

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1990
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  - conf/eurodac/ErnstSJT90
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Rolf Ernst, S. Sutarwala, J.-Y. Jou, M. Tong:
Simulation based verification of register-transfer level behavioral synthesis tools. EURO-DAC 1990: 396-400

1980 – 1989

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1989
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Rolf Ernst, S. Sutarwala, J.-Y. Jou:
TSG: A Test System Generator for Debugging and Regression Test of High-Level Behavioral Synthesis Tools. ITC 1989: 937
1988
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  - journals/ipl/BalakrishnanSMBL88
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M. Balakrishnan, S. Sutarwala, Arun K. Majumdar, Dilip K. Banerji, James G. Linders:
A Semantic Approach for Modular Synthesis of VLSI Systems. Inf. Process. Lett. 27(1): 1-7 (1988)

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