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ORCIDDilip K. Banerji
Person information
- affiliation: University of Guelph, ON, Canada
- affiliation (PhD 1971): University of Waterloo, ON, Canada
- affiliation (former): University of Ottawa, ON, Canada
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2010 – 2019
- 2011
[j16]Nikhil Saxena, Mieso K. Denko, Dilip K. Banerji:
A hierarchical architecture for detecting selfish behaviour in community wireless mesh networks. Comput. Commun. 34(4): 548-555 (2011)
2000 – 2009
- 2009
- [j15]Shawki Areibi, X. Bao, Gary Gréwal, Dilip K. Banerji, Peng Du:
Meta-Heuristic Based Techniques for FPGA Placement: A Study. Int. J. Comput. Their Appl. 16(1): 13-33 (2009) - [c20]Ming Xu, Gary Gréwal, Shawki Areibi, Charlie Obimbo, Dilip K. Banerji:
Near-linear wirelength estimation for FPGA placement. CCECE 2009: 1198-1203 - 2007
- [j14]Gary Gréwal, Stelian Coros
, Dilip K. Banerji, Andrew Morton:
Assigning data to dual memory banks in DSPs with a genetic algorithm using a repair heuristic. Appl. Intell. 26(1): 53-67 (2007) - 2006
- [c19]Gary Gréwal, Stelian Coros, Dilip K. Banerji, Andrew Morton:
Comparing a Genetic Algorithm Penalty Function and Repair Heuristic in the DSP Application Domain. Artificial Intelligence and Applications 2006: 31-39 - [c18]Shouvik Chowdhury, Gary William Grewal, Dilip K. Banerji:
Clustering Hanan Points to Reduce Vlsi Interconnect Routing Times. CCECE 2006: 1223-1227 - [c17]Gary Gréwal, Stelian Coros, Dilip K. Banerji, Andrew Morton, Mario Ventresca:
Optimized Memory Assignment for DSPs. IEEE Congress on Evolutionary Computation 2006: 64-72 - 2004
- [c16]Peng Du, Gary William Grewal, Shawki Areibi, Dilip K. Banerji:
A Fast Hierarchical Approach to FPGA Placement. ESA/VLSI 2004: 497-503 - [c15]Gary William Grewal, Thomas Charles Wilson, Ming Xu, Dilip K. Banerji:
Shrubbery: A New Algorithm for Quickly Growing High-Quality Steiner Trees. VLSI Design 2004: 855-862 - 2003
- [c14]Zhibin Dai, Dilip K. Banerji:
Routability Prediction for Field Programmable Gate Arrays with a Routing Hierarchy. VLSI Design 2003: 85-90
1990 – 1999
- 1999
- [c13]Wei Li, Dilip K. Banerji:
Routability Prediction for Hierarchical FPGAs. Great Lakes Symposium on VLSI 1999: 256-259 - 1996
- [j13]Anupam Basu, Dilip K. Banerji, Amit Basu, Thomas Charles Wilson, Jayanti C. Majithia:
A Modified Approach to Test Plan Generation for Combinational Logic Blocks. VLSI Design 4(3): 243-256 (1996) - [c12]J. Shu, Thomas Charles Wilson, Dilip K. Banerji:
Instruction-Set Matching and GA-based Selection for Embedded-Processor Code Generation. VLSI Design 1996: 73-76 - 1995
- [j12]Thomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji:
An ILP Solution for Optimum Scheduling, Module and Register Allocation, and Operation Binding in Datapath Synthesis. VLSI Design 3(1): 21-36 (1995) - 1994
- [c11]Thomas Charles Wilson, Gary William Grewal, Shawn Henshall, Dilip K. Banerji:
An ILP-based approach to code generation. Code Generation for Embedded Processors 1994: 103-118 - [c10]Thomas Charles Wilson, Gary William Grewal, Dilip K. Banerji:
An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis. ICCD 1994: 581-586 - [c9]Thomas Charles Wilson, Gary Gréwal, Ben Halley, Dilip K. Banerji:
An integrated approach to retargetable code generation. HLSS 1994: 70-75 - 1993
- [c8]Thomas Charles Wilson, Manoj K. Garg, R. Deadman, Ben Halley, Dilip K. Banerji:
MinMux: a new approach for global minimization of multiplexers in interconnect synthesis. Great Lakes Symposium on VLSI 1993: 132-138 - [c7]Thomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji:
An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis. VLSI Design 1993: 192-197 - 1992
- [c6]Anupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia:
An Approach to Minimize Testability Overhead for BILBO based Built-In-Self-Test. VLSI Design 1992: 354-355 - 1991
- [c5]Thomas Charles Wilson, Anupam Basu, Dilip K. Banerji, Jayanti C. Majithia:
Test plan generation and concurrent scheduling of tests in the presence of conflicts. Great Lakes Symposium on VLSI 1991: 243-248 - [c4]Anupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia:
Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits. Great Lakes Symposium on VLSI 1991: 340-341
1980 – 1989
- 1988
- [j11]M. Balakrishnan, S. Sutarwala, Arun K. Majumdar, Dilip K. Banerji, James G. Linders:
A Semantic Approach for Modular Synthesis of VLSI Systems. Inf. Process. Lett. 27(1): 1-7 (1988) - [j10]M. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders:
Synthesis of decentralised controllers from high level description. Microprocess. Microprogramming 22(3): 217-229 (1988) - [j9]M. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders, Jayanti C. Majithia:
Allocation of multiport memories in data path synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(4): 536-540 (1988) - 1986
- [j8]S. P. Rana, Dilip K. Banerji:
An optimal distributed solution to the dining philosophers problem. Int. J. Parallel Program. 15(4): 327-335 (1986) - 1984
- [j7]Dilip K. Banerji, Saroj Kaushik:
On Combinational Logic for Sign Detection in Residue Number Systems. Aust. Comput. J. 16(3): 90-95 (1984) - 1983
- [c3]Dilip K. Banerji, Saroj Kaushik:
Representation and processing of fractions in a residue system. IEEE Symposium on Computer Arithmetic 1983: 29-36
1970 – 1979
- 1976
- [j6]Jacques Raymond, Dilip K. Banerji:
Using a Microprocessor in an Intelligent Graphics Terminal. Computer 9(4): 18-25 (1976) - 1975
- [c2]Dilip K. Banerji:
On combinational logic for sign detection in residue number systems. IEEE Symposium on Computer Arithmetic 1975: 113-116 - 1974
- [j5]Dilip K. Banerji:
A Novel Implementation Method for Addition and Subtraction in Residue Number Systems. IEEE Trans. Computers 23(1): 106-109 (1974) - [j4]Dilip K. Banerji:
On the Use of Residue Arithmetic for Computation. IEEE Trans. Computers 23(12): 1315-1317 (1974) - 1973
- [j3]S. R. Das, Dilip K. Banerji, A. Chattopadhyay:
On Control Memory Minimization in Microprogrammed Digital Computers. IEEE Trans. Computers 22(9): 845-848 (1973) - 1972
- [j2]Dilip K. Banerji, Janusz A. Brzozowski:
On Translation Algorithms in Residue Number Systems. IEEE Trans. Computers 21(12): 1281-1285 (1972) - [c1]Dilip K. Banerji:
"A novel implementation method for addition and subtraction in residue number systems". IEEE Symposium on Computer Arithmetic 1972: 1-15
1960 – 1969
- 1969
- [j1]Dilip K. Banerji, Janusz A. Brzozowski:
Sign Detection in Residue Number Systems. IEEE Trans. Computers 18(4): 313-320 (1969)
Coauthor Index
aka: Gary Gréwal
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