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Hyung-Sik Won

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2010 – 2019

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2012
[c2]
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  dblp key:
  - conf/isscc/LimJWLKKCKKPJ12
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  persistent URL:
  - https://dblp.org/rec/conf/isscc/LimJWLKKCKKPJ12
Kyu-Nam Lim, Woong-Ju Jang, Hyung-Sik Won, Kang-Yeol Lee, Hyungsoo Kim, Dong-Whee Kim, Mi-Hyun Cho, Seung-Lo Kim, Jong-Ho Kang, Keun-Woo Park, Byung-Tae Jeong:
A 1.2V 23nm 6F² 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture. ISSCC 2012: 42-44
2010
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  - conf/isscc/LeeKWLP10
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Myoung Jin Lee, Ki Myung Kyung, Hyung-Sik Won, Myoung Su Lee, Kun Woo Park:
A bitline sense amplifier for offset compensation. ISSCC 2010: 438-439

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