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ORCIDISSCC 2012: San Francisco, CA, USA
- 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012. IEEE 2012, ISBN 978-1-4673-0376-7
Paper Sessions
Plenary Session
- Anantha P. Chandrakasan, Hideto Hidaka:
Session 1 overview: Plenary session. 7-9 - Eli Harari:
Flash memory - The great disruptor! 10-15 - Carmelo Papa:
The role of semiconductors in the energy landscape. 16-21 - Yoichi Yano:
Take the expressway to go greener. 24-30 - David Perlmutter:
Sustainability in silicon and systems development. 31-35
High-Bandwidth DRAM & PRAM
- Joo-Sun Choi, Daisaburo Takashima:
Session 2 overview: High-bandwidth DRAM & PRAM: Memory subcommittee. 36-37 - Kyomin Sohn, Taesik Na, Indal Song, Yong Shim, Wonil Bae, Sanghee Kang, Dongsu Lee, Hangyun Jung, Hanki Jeoung, Ki Won Lee, Junsuk Park, Jongeun Lee, Byunghyun Lee, Inwoo Jun, Juseop Park, Junghwan Park, Hundai Choi, Sanghee Kim, Haeyoung Chung, Young Choi, Dae-Hee Jung, Jang Seok Choi, Byung-Sick Moon, Jung-Hwan Choi, Byungchul Kim, Seong-Jin Jang, Joo-Sun Choi, Kyungseok Oh:
A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme. 38-40 - Kibong Koo, Sunghwa Ok, Yonggu Kang, Seungbong Kim, Choungki Song, Hyeyoung Lee, Hyungsoo Kim, Yongmi Kim, Jeonghun Lee, Seunghan Oak, Yosep Lee, Jungyu Lee, Joongho Lee, Hyungyu Lee, Jaemin Jang, Jongho Jung, Byeongchan Choi, Yong-Ju Kim, Youngdo Hur, Yunsaing Kim, Byong-Tae Chung, Yongtak Kim:
A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture. 40-41 - Kyu-Nam Lim, Woong-Ju Jang, Hyung-Sik Won, Kang-Yeol Lee, Hyungsoo Kim, Dong-Whee Kim, Mi-Hyun Cho, Seung-Lo Kim, Jong-Ho Kang, Keun-Woo Park, Byung-Tae Jeong:
A 1.2V 23nm 6F2 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture. 42-44 - Yong-Cheol Bae, Joon-Young Park, Sang Jae Rhee, Seung-Bum Ko, Yonggwon Jeong, Kwang-Sook Noh, Young Hoon Son, Jaeyoun Youn, Yonggyu Chu, Hyunyoon Cho, Mijo Kim, Daesik Yim, Hyo-Chang Kim, Sang-Hoon Jung, Hye-In Choi, Sungmin Yim, Jung-Bae Lee, Joo-Sun Choi, Kyungseok Oh:
A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme. 44-46 - Youngdon Choi, Ickhyun Song
, Mu-Hui Park, Hoeju Chung, Sanghoan Chang, Beakhyoung Cho, Jinyoung Kim, Younghoon Oh, Dukmin Kwon, Jung Sunwoo, Junho Shin, Yoohwan Rho, Changsoo Lee, Min Gu Kang, Jaeyun Lee, Yongjin Kwon, Soehee Kim, Jaewhan Kim, Yong-jun Lee, Qi Wang, Sooho Cha, Sujin Ahn, Hideki Horii, Jaewook Lee, KiSeung Kim, Han-Sung Joo, KwangJin Lee, Yeong-Taek Lee, Jei-Hwan Yoo, Gitae Jeong:
A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth. 46-48 - Hyun-Woo Lee, Soo-Bin Lim, Junyoung Song, Jabeom Koo, Dae-Han Kwon, Jong-Ho Kang, Yunsaing Kim, Young-Jung Choi, Kunwoo Park, Byong-Tae Chung, Chulwoo Kim:
A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface. 48-50 - Yanghyo Kim, Gyungsu Byun, Adrian Tang, Chewnpu Jou, Hsieh-Hung Hsieh, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang:
An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression. 50-52 - Won-Joo Yun, Shinya Nakano, Wataru Mizuhara, Atsutake Kosuge, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line. 52-54
Processors
- Joshua Friedrich, Jinuk Luke Shin:
Session 3 overview: Processors: High performance digital subcommittee. 54-55 - Satish Damaraju, George Varghese, Sanjeev Jahagirdar, Tanveer Khondker, Robert Milstrey, Sanjib Sarkar, Scott Siers, Israel Stolero, Arun Subbiah:
A 22nm IA multi-CPU and GPU System-on-Chip. 56-57 - Brian Miller, Derek Brasili, Tim Kiszely, Rob Kuhn, Rahul Mehrotra, Manan Salvi, Mandar Kulkarni, Anand Varadharajan, Shi-Huang Yin, William Lin, Adam Hughes, Bill Stysiack, Vasu Kandadi, Ilan Pragaspathi, Dan Hartman, David Carlson, Vishnu Yalala, Thucydides Xanthopoulos, Scott E. Meninger, Ethan Crain, Mark Spaeth, Akin Aina, Suresh Balasubramanian, Joe Vulih, Pragati Tiwary, David Lin, Richard Kessler, Bruce Fishbein, Anil Jain:
A 32-core RISC microprocessor with network accelerators, power management and testability features. 58-60 - Jinuk Luke Shin, Heechoul Park, Hongping Penny Li, Alan P. Smith, Youngmoon Choi, Harikaran Sathianathan, Sudesna Dash, Sebastian Turullols, Song Kim, Robert P. Masleid, Georgios K. Konstadinidis, Robert T. Golla, Mary Jo Doherty, Greg Grohoski, Curtis McAllister:
The next-generation 64b SPARC core in a T4 SoC processor. 60-62 - Hasnain Lakdawala, Mark Schaecher, Chang-Tsung Fu, Rahul Dilip Limaye, Jon Duster, Yulin Tan, Ajay Balankutty, Erkan Alpman, Chun C. Lee, Satoshi Suzuki, Brent R. Carlton, Hyung Seok Kim, Marian Verhelst, Stefano Pellerano, Tong Kim, Durgesh Srivastava, Satish Venkatesan, Hyung-Jin Lee, Peter Vandervoorn, Jad Rizk, Chia-Hong Jan, Krishnamurthy Soumyanath, Sunder Ramamurthy:
32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver. 62-64 - Zhiyi Yu, Kaidi You, Ruijin Xiao, Heng Quan, Peng Ou, Yan Ying, Haofan Yang, Ming-e Jing, Xiaoyang Zeng:
An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms. 64-66 - Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Saurabh Dighe, Gregory Ruhl, Paolo A. Aseron, Howard Wilson, Nitin Borkar, Vivek De, Shekhar Borkar:
A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. 66-68 - Visvesh S. Sathe, Srikanth Arekapudi, Charles Ouyang, Marios C. Papaefthymiou, Alexander T. Ishii, Samuel Naffziger:
Resonant clock design for a power-efficient high-volume x86-64 microprocessor. 68-70 - Y. William Li, Carlos Ornelas, Hyung Seok Kim, Hasnain Lakdawala, Ashoke Ravi, Krishnamurthy Soumyanath:
A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS. 70-72 - Masoud Zargari, Songcheol Hong:
Session 4 overview: RF techniques: RF subcommittee. 72-73
RF Techniques
- David Murphy, Amr Hafez, Ahmad Mirzaei, Mohyee Mikhemar, Hooman Darabi, Mau-Chung Frank Chang, Asad A. Abidi:
A blocker-tolerant wideband noise-cancelling receiver with a 2dB noise figure. 74-76 - Amir Ghaffari, Eric A. M. Klumperink, Bram Nauta:
8-Path tunable RF notch filters for blocker suppression. 76-78 - Wei Cheng, Mark S. Oude Alink, Anne-Johan Annema, Gerard Wienk, Bram Nauta:
A wideband IM3 cancellation technique for CMOS attenuators. 78-80 - Seyed Kasra Garakoui, Eric A. M. Klumperink, Bram Nauta, Frank E. van Vliet:
A 1-to-2.5GHz phased-array IC based on gm-RC all-pass time-delay cells. 80-82 - Bonhoon Koo, Taehwan Joo, Yoosam Na, Songcheol Hong:
A fully integrated dual-mode CMOS power amplifier for WCDMA applications. 82-84 - Shouhei Kousai, Kohei Onizuka, Takashi Yamaguchi, Yasuhiko Kuriyama, Masami Nagaoka:
A 28.3mW PA-closed loop for linearity and efficiency improvement integrated in a +27.1dBm WCDMA CMOS power amplifier. 84-86 - Kouichi Kanda, Yoichi Kawano, Takao Sasaki, Noriaki Shirai, Tetsuro Tamura, Shigeaki Kawai, Masahiro Kudo, Tomotoshi Murakami, Hiroyuki Nakamoto, Nobumasa Hasegawa, Hideki Kano, Nobuhiro Shimazui, Akiko Mineyama, Kazuaki Oishi, Masashi Shima, Naoyoshi Tamura, Toshihide Suzuki, Toshihiko Mori, Kimitoshi Niratsuka, Shinji Yamaura:
A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets. 86-88 - Ioannis Sarkas, Andreea Balteanu, Eric Dacquay, Alexander Tomkins, Sorin P. Voinigescu:
A 45nm SOI CMOS Class-D mm-Wave PA with >10Vpp differential swing. 88-90
Audio and Power Converters
- Wing-Hung Ki, Jed Hurwitz:
Session 5 overview: Audio and power converters: Analog subcommittee. 90-91 - Angelo Nagari, Emmanuel Allier, Francois Amiard, Vincent Binet, Christian Fraisse:
An 8Ω 2.5W 1%-THD 104dB(A)-dynamic-range Class-D audio amplifier with an ultra-low EMI system and current sensing for speaker protection. 92-94 - Bert Serneels, Eldert Geukens, Bram De Muer, Tim Piessens:
A 1.5W 10V-output Class-D amplifier using a boosted supply from a single 3.3V input in standard 1.8V/3.3V 0.18μm CMOS. 94-96 - Sunwoo Kwon, Injeong Kim, Shinyoung Yi, Sangheyub Kang, Sangheon Lee, Taeho Hwang, Byoungkwon Moon, Yunyoung Choi, Hosung Sung, Jinseok Koh:
A 0.028% THD+N, 91% power-efficiency, 3-level PWM Class-D amplifier with a true differential front-end. 96-98 - Gerard Villar Pique:
A 41-phase switched-capacitor power converter with 3.8mV output ripple and 81% efficiency in baseline 90nm CMOS. 98-100 - Jason T. Stauth, Michael D. Seeman, Kapil Kesarwani:
A high-voltage CMOS IC and embedded system for distributed photovoltaic energy optimization with over 99% effective conversion efficiency and insertion loss below 0.1%. 100-102 - Reinhard Enne, Miodrag Nikolic, Horst Zimmermann:
A maximum power-point tracker without digital signal processing in 0.35μm CMOS for automotive applications. 102-104 - Jong-Pil Im, Se-Won Wang, Kang-Ho Lee, Young-Jin Woo, Young-sub Yuk, Tae-Hwang Kong, Sung-Wan Hong, Seung-Tak Ryu, Gyu-Hyeong Cho:
A 40mV transformer-reuse self-startup boost converter with MPPT control for thermoelectric energy harvesting. 104-106 - Karthik Kadirvel, Yogesh K. Ramadass, Umar Lyles, John Carpenter, Vadim Ivanov, Vince McNeil, Anantha P. Chandrakasan, Brian Lum-Shue-Chan:
A 330nA energy-harvesting charger with battery management for solar and thermoelectric energy harvesting. 106-108
Medical, Displays and Imagers
- Yusuke Oike, Maysam Ghovanloo:
Session 6 overview: Medical, displays and imagers: Imagers, MEMS, medical and displays subcommittee. 108-109 - Hyunsik Kim, Sang-Wook Han, Junhyeok Yang, Sung-il Kim, Young Kim, Sangwook Kim, Dae-Kun Yoon, Jun Su Lee, Jae-Chul Park, Younghun Sung, Seong-Deok Lee, Seung-Tak Ryu, Gyu-Hyeong Cho:
A sampling-based 128×128 direct photon-counting X-ray image sensor with 3 energy bins and spatial resolution of 60μm/pixel. 110-112 - Jaehyuk Choi, Seokjun Park, Jihyun Cho, Euisik Yoon:
A 1.36μW adaptive CMOS image sensor with reconfigurable modes of operation from available energy/illumination for distributed wireless sensor network. 112-114 - Meng-Ting Chung, Chih-Cheng Hsieh:
A 0.5V 4.95μW 11.8fps PWM CMOS imager with 82dB dynamic range and 0.055% fixed-pattern noise. 114-116 - Kiduk Kim, San-Ho Byun, Yoon-Kyung Choi, Jong-Hak Baek, Hwa-Hyun Cho, Jong Kang Park, Hae-Yong Ahn, Chang-Ju Lee, Min-Soo Cho, Joo-Hyeon Lee, Sang-Woo Kim, Hyung-Dal Kwon, Yong-Yeob Choi, Hosuk Na, Junchul Park, Yeon-Joong Shin, Kyungsuk Jang, Gyoocheol Hwang, Myunghee Lee:
A capacitive touch controller robust to display noise for ultrathin touch screen displays. 116-117 - Nick Van Helleputte, Sunyoung Kim, Hyejung Kim, Jong Pal Kim, Chris Van Hoof, Refet Firat Yazicioglu:
A 160μA biopotential acquisition ASIC with fully integrated IA and motion-artifact suppression. 118-120 - Kang-Ho Lee, Sukhwan Choi, Jeong Oen Lee, Jun-Bo Yoon, Gyu-Hyeong Cho:
CMOS capacitive biosensor with enhanced sensitivity for label-free DNA detection. 120-122 - David Tyndall, Bruce Rae, David Day-Uei Li, Justin A. Richardson, Jochen Arlt, Robert K. Henderson:
A 100Mphoton/s time-resolved mini-silicon photomultiplier with on-chip fluorescence lifetime estimation in 0.13μm CMOS imaging technology. 122-124 - Hangue Park, Benoit Gosselin, Mehdi Kiani, Hyung-Min Lee, Jeonghee Kim, Xueliang Huo, Maysam Ghovanloo:
A wireless magnetoresistive sensing system for an intra-oral tongue-computer interface. 124-126 - Simone Gambini, Karl Skucha, Paul Peng Liu, Jungkyu Kim, Reut Krigel, Richard Mathies, Bernhard E. Boser:
A CMOS 10kpixel baseline-free magnetic bead detector with column-parallel readout for miniaturized immunoassays. 126-128
Multi Gb/s Receiver and Parallel I/O Techniques
- Robert Payne, Tatsuya Saito:
Session 7 overview: Multi-Gb/s receiver and parallel I/O techniques: Wireline subcommittee. 128-129 - Meisam Honarvar Nazari, Azita Emami-Neyestanak:
An 18.6Gb/s double-sampling receiver in 65nm CMOS for ultra-low-power optical communication. 130-131 - Kambiz Kaviani, Amir Amirkhany, Charlie Huang, Phuong Le, Chris J. Madden, Keisuke Saito, Koji Sano, Vinod Murugan, Wendemagegnehu T. Beyene, Ken Chang, Chuck Yuan:
A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration. 132-134 - Ankur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman:
A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS. 134-136 - Young-Sik Kim, Seon-Kyoo Lee, Seung-Jun Bae, Young-Soo Sohn, Jung-Bae Lee, Joo-Sun Choi, Hong-June Park, Jae-Yoon Sim:
An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface. 136-138 - Amir Amirkhany, Kambiz Kaviani, Ali-Azam Abbasfar, H. Md. Shuaeb Fazeel, Wendemagegnehu T. Beyene, Chikara Hoshino, Chris J. Madden, Ken Chang, Chuck Yuan:
A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical link. 138-140 - Seon-Kyoo Lee, Hyunsoo Ha, Hong-June Park, Jae-Yoon Sim:
A 5Gb/s single-ended parallel receiver with adaptive FEXT cancellation. 140-142 - Yong Liu, Wing K. Luk, Daniel J. Friedman:
A compact low-power 3D I/O in 45nm CMOS. 142-144
Delta-Sigma Converters
- Brian Brandt, Gerhard Mitteregger:
Session 8 overview: Delta-sigma converters: Data converters subcommittee. 144-145 - Jeffrey Harrison, Michal Nesselroth, Robert Mamuad, Arya Behzad, Andrew Adams, Steve Avery:
An LC bandpass ΔΣ ADC with 70dB SNDR over 20MHz bandwidth using CMOS DACs. 146-148 - Hyungil Chae, Jaehun Jeong, Gabriele Manganaro, Michael P. Flynn:
A 12mW low-power continuous-time bandpass ΔΣ modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF. 148-150 - Hajime Shibata, Richard Schreier, Wenhua Yang, Ali Shaikh, Donald Paterson, Trevor C. Caldwell, David Alldred, Ping Wing Lai:
A DC-to-1GHz tunable RF ΔΣ ADC achieving DR = 74dB and BW = 150MHz at f0 = 450MHz using 550mW. 150-152 - Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu:
A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer. 152-154 - Pascal Witte, John G. Kauffman, Joachim Becker, Yiannos Manoli, Maurits Ortmanns:
A 72dB-DR ΔΣ CT modulator using digitally estimated auxiliary DAC linearization achieving 88fJ/conv in a 25MHz BW. 154-156 - Pradeep Shettigar, Shanthi Pavan:
A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS. 156-158 - Venkatesh Srinivasan, Victoria Wang, Patrick Satarzadeh, Baher Haroun, Marco Corsi:
A 20mW 61dB SNDR (60MHz BW) 1b 3rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS. 158-160
Wireless Transceiver Techniques
- Sven Mattisson, Shouhei Kousai:
Session 9 overview: Wireless transceiver techniques: Wireless subcommittee. 160-161 - Jody Greenberg, Fernando De Bernardinis, Carlo Tinella, Antonio Milani, Johnny Pan, Paola Uggetti, Marco Sosio, Shaoan Dai, Sam Tang, Giovanni Cesura, Gabriele Gandolfi, Vittorio Colonna, Rinaldo Castello:
A 40MHz-to-1GHz fully integrated multistandard silicon tuner in 80nm CMOS. 162-164 - Omid Oliaei, Mark Kirschenmann, David Newman, Kurt Hausmann, Haolu Xie, Patrick Rakers, Mahib Rahman, Michael Gomez, Chuanzhao Yu, Benjamin Gilsdorf, Kurt Sakamoto:
A multiband multimode transmitter without driver amplifier. 164-166 - Shadi Youssef, Ronan A. R. van der Zee, Bram Nauta:
Active feedback receiver with integrated tunable RF channel selectivity, distortion cancelling, 48dB stopband rejection and >+12dBm wideband IIP3, occupying 2 in 65nm CMOS. 166-168 - Paolo Madoglio, Ashoke Ravi, Hongtao Xu, Kailash Chandrashekar, Marian Verhelst, Stefano Pellerano, Luis Cuellar, Mariano Aguirre, Masoud Sajadieh, Ofir B. Degani, Hasnain Lakdawala, Yorgos Palaskas:
A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS. 168-170 - Dixian Zhao, Shailesh Kulkarni, Patrick Reynaert:
A 60GHz outphasing transmitter in 40nm CMOS with 15.6dBm output power. 170-172 - Yuan-Hung Chung, Min Chen, Wei-Kai Hong, Jie-Wei Lai, Sheng-Jau Wong, Chien-Wei Kuan, Hong-Lin Chu, Chihun Lee, Chih-Fan Liao, Hsuan-Yu Liu, Hong-Kai Hsu, Li-Chun Ko, Kuo-Hao Chen, Chao-Hsin Lu, Tsung-Ming Chen, YuLi Hsueh, Chunwei Chang, Yi-Hsien Cho, Chih-Hsien Shen, Yuan Sun, Eng-Chuan Low, Xudong Jiang, Deyong Hu, Weimin Shu, Jhy-Rong Chen, Jui-Lin Hsu, Chia-Jui Hsu, Jing-Hong Conan Zhan, Osama Shana'a, Guang-Kaai Dehng, George Chien:
A 4-in-1 (WiFi/BT/FM/GPS) connectivity SoC with enhanced co-existence performance in 65nm CMOS. 172-174 - Michiel C. M. Soer, Eric A. M. Klumperink, Bram Nauta, Frank E. van Vliet:
A 1.5-to-5.0GHz input-matched +2dBm P1dB all-passive switched-capacitor beamforming receiver front-end in 65nm CMOS. 174-176
High-Performance Digital
- Lew Chua-Eoan, Se-Hyun Yang:
Session 10 overview: High-performance digital: High performance digital subcommittee. 176-177 - Steven Hsu, Amit Agarwal, Mark A. Anders, Sanu Mathew, Himanshu Kaul, Farhana Sheikh, Ram Krishnamurthy:
A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS. 178-180 - Dennis Walter, Sebastian Höppner, Holger Eisenreich, Georg Ellguth, Stephan Henker, Stefan Hänzsche, René Schüffny, Markus Winter, Gerhard P. Fettweis:
A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS. 180-182 - Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar:
A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS. 182-184 - Farhana Sheikh, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar:
A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS. 184-186 - Matt Wordeman, Joel Silberman, Gary W. Maier, Michael Scheuermann:
A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias. 186-187 - Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim:
3D-MAPS: 3D Massively parallel processor with stacked memory. 188-190 - David Fick, Ronald G. Dreslinski, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw:
Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores. 190-192 - Hiroyuki Miyazaki, Yoshihiro Kusano, Hiroshi Okano, Tatsumi Nakada, Ken Seki, Toshiyuki Shimizu, Naoki Shinjo, Fumiyoshi Shoji, Atsuya Uno, Motoyoshi Kurokawa:
K computer: 8.162 PetaFLOPS massively parallel scalar supercomputer built with over 548k cores. 192-194
Sensors & MEMs
- Christoph Hagleitner, Maurits Ortmanns:
Session 11 overview: Sensors and MEMS: Imagers, MEMS, medical and displays subcommittee. 194-195 - Pedram Lajevardi, Vladimir P. Petkov, Boris Murmann:
A ΔΣ interface for MEMS accelerometers using electrostatic spring-constant modulation for cancellation of bondwire capacitance drift. 196-198 - Sha Xia, Kofi A. A. Makinwa, Stoyan N. Nihtianov:
A capacitance-to-digital converter for displacement sensing with 17b resolution and 20μs conversion time. 198-200 - Jeroen van den Boom:
A 50μW biasing feedback loop with 6ms settling time for a MEMS microphone with digital output. 200-202 - Marko Rocznik, Fabian Henrici, Remigius Has:
ASIC for a resonant wireless pressure-sensing system for harsh environments achieving ±2% error between -40 and 150°C using Q-based temperature compensation. 202-204 - Caspar P. L. van Vroonhoven, Dan d'Aquino, Kofi A. A. Makinwa:
A ±0.4°C (3σ) -70 to 200°C time-domain temperature sensor based on heat diffusion in Si and SiO2. 204-206 - Michael H. Perrott, Jim Salvia, Fred S. Lee, Aaron Partridge, Shouvik Mukherjee, Carl Arft, Jin-Tae Kim, Niveditha Arumugam, Pavan Gupta, Sassan Tabatabaei, Sudhakar Pamarti, Haechang Lee, Fari Assaderaghi:
A temperature-to-digital converter for a MEMS-based programmable oscillator with better than ±0.5ppm frequency stability. 206-208 - Kamran Souri, Youngcheol Chae, Kofi A. A. Makinwa:
A CMOS temperature sensor with a voltage-calibrated inaccuracy of ±0.15°C (3σ) from -55 to 125°C. 208-210 - Joseph Shor, Kosta Luria, Dror Zilberman:
Ratiometric BJT-based thermal sensor in 32nm and 22nm technologies. 210-212
Multimedia & Communications SoCs
- Byeong-Gyu Nam, Shannon Morton:
Session 12 overview: Multimedia and communications SoCs: Energy-efficient digital subcommittee. 212-213 - Se-Hyun Yang, Seogjun Lee, Jae Young Lee, Jeonglae Cho, Hoi-Jin Lee, Dongsik Cho, Junghun Heo, Sunghoon Cho, Youngmin Shin, Sunghee Yun, Euiseok Kim, Ukrae Cho, Edward Pyo, Man Hyuk Park, Jae-Cheol Son, Chinhyun Kim, Jeongnam Youn, Youngki Chung, Sungho Park, Seung Ho Hwang:
A 32nm high-k metal gate application processor with GHz multi-core CPU. 214-216 - Markus Winter, Steffen Kunze, Esther P. Adeva, Björn Mennenga, Emil Matús, Gerhard P. Fettweis, Holger Eisenreich, Georg Ellguth, Sebastian Höppner, Stefan Scholze, René Schüffny, Tomoyoshi Kobori:
A 335Mb/s 3.9mm2 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates. 216-218 - Kenichi Okada, Keitarou Kondou, Masaya Miyahara, Masashi Shinagawa, Hiroki Asada, Ryo Minami, Tatsuya Yamaguchi, Ahmed Musa, Yuuki Tsukui, Yasuo Asakura, Shinya Tamonoki, Hiroyuki Yamagishi, Yasufumi Hino, Takahiro Sato, Hironori Sakaguchi, Naoki Shimasaki, Toshihiko Ito, Yasuaki Takeuchi, Ning Li, Qinghong Bu, Rui Murakami, Keigo Bunsen, Kota Matsushita, Makoto Noda, Akira Matsuzawa:
A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry. 218-220 - Jinwook Oh, Gyeonghoon Kim, Junyoung Park, Injoon Hong, Seungjin Lee, Hoi-Jun Yoo:
A 320mW 342GOPS real-time moving object recognition processor for HD 720p video streams. 220-222 - Yasuki Tanabe, Masato Sumiyoshi, Manabu Nishiyama, Itaru Yamazaki, Shinsuke Fujii, Katsuyuki Kimura, Takuma Aoyama, Moriyasu Banno, Hiroo Hayashi, Takashi Miyamori:
A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications. 222-223 - Dajiang Zhou, Jinjia Zhou, Jiayi Zhu, Peilin Liu, Satoshi Goto:
A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications. 224-226 - Mahesh Mehendale, Subrangshu Das, Mohit Sharma, Mihir N. Mody, Ratna Reddy, Joseph P. Meehan, Hideo Tamama, Brian Carlson, Mike Polley:
A true multistandard, programmable, low-power, full HD video-codec engine for smartphone SoC. 226-228
High-Performance Embedded SRAM
- Leland Chang, Michael Clinton:
Session 13 overview: High-performance embedded SRAM: Memory subcommittee. 228-229 - Eric Karl, Yih Wang, Yong-Gee Ng, Zheng Guo, Fatih Hamzaoglu, Uddalak Bhattacharya, Kevin Zhang, Kaizad Mistry, Mark Bohr:
A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry. 230-232