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Journal Articles
- 2020
[j25]Yan He
, Zhijian Chen, Xiaoyan Xiang, Tao-Tao Zhu:
A Dedicated Greedy Short Path Padding Solution Method for Error Resilient Circuit Designs. IEEE Access 8: 190251-190262 (2020)- [j24]Jiaquan Wu, Feiteng Li, Zhijian Chen, Xiaoyan Xiang, Yu Pu:
Patient-Specific ECG Classification with Integrated Long Short-Term Memory and Convolutional Neural Networks. IEICE Trans. Inf. Syst. 103-D(5): 1153-1163 (2020) - 2019
- [j23]Huibin Wang, Chunqiang Li, Jianyi Meng, Xiaoyan Xiang:
SCSE: Boosting Symbolic Execution via State Concretization. IEICE Trans. Inf. Syst. 102-D(8): 1506-1516 (2019) - [j22]Menghan Jia, Feiteng Li, Zhijian Chen, Xiaoyan Xiang, Xiaolang Yan:
High Noise Tolerant R-Peak Detection Method Based on Deep Convolution Neural Network. IEICE Trans. Inf. Syst. 102-D(11): 2272-2275 (2019) - [j21]Jiaquan Wu, Feiteng Li, Zhijian Chen, Xiaoyan Xiang:
A 3.89-GOPS/mW Scalable Recurrent Neural Network Processor With Improved Efficiency on Memory and Computation. IEEE Trans. Very Large Scale Integr. Syst. 27(12): 2939-2943 (2019) - 2018
- [j20]Zhijian Chen, Menghan Jia, Jiahui Luo, Tao-Tao Zhu, Xiaoyan Xiang, Jianyi Meng:
A low power QRS detection processor with adaptive scaling of processing resolution. IEICE Electron. Express 15(1): 20170882 (2018) - [j19]Yan He, Jianyi Meng, Zhijian Chen, Xiaoyan Xiang, Chen Chen:
An effectiveness-oriented greedy heuristic for padding short paths in ultra-low supply voltage designs. IEICE Electron. Express 15(3): 20171229 (2018) - [j18]Yin Xu, Zhijian Chen, Xiaoyan Xiang, Jianyi Meng:
An energy-efficient parallel VLSI architecture for SVM classification. IEICE Electron. Express 15(7): 20180099 (2018) - [j17]Jiahui Luo, Zhijian Chen, Xiaoyan Xiang, Jianyi Meng:
A Highly Adaptive Lossless ECG Compression ASIC for Wireless Sensors Based on Hybrid Gomlomb Coding. IEICE Trans. Inf. Syst. 101-D(3): 791-794 (2018) - [j16]Yande Xiang, Jiahui Luo, Tao-Tao Zhu, Sheng Wang, Xiaoyan Xiang, Jianyi Meng:
ECG-Based Heartbeat Classification Using Two-Level Convolutional Neural Network and RR Interval Difference. IEICE Trans. Inf. Syst. 101-D(4): 1189-1198 (2018) - [j15]Zhijian Chen, Jiahui Luo, Kaiwen Lin, Jiaquan Wu, Tao-Tao Zhu, Xiaoyan Xiang, Jianyi Meng:
An Energy-Efficient ECG Processor With Weak-Strong Hybrid Classifier for Arrhythmia Detection. IEEE Trans. Circuits Syst. II Express Briefs 65-II(7): 948-952 (2018) - 2017
- [j14]Tao-Tao Zhu, Xiaoyan Xiang, Chen Chen, Jianyi Meng:
SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor. IEICE Electron. Express 14(8): 20170218 (2017) - [j13]Sheng Wang, Chen Chen, Xiaoyan Xiang, Jianyi Meng:
A metastability-immune error-resilient flip-flop for near-threshold variation-tolerant designs. IEICE Electron. Express 14(11): 20170353 (2017) - [j12]Jiahui Luo, Zhijian Chen, Xiaoyan Xiang, Jianyi Meng, Haibin Shen:
A dual-mode ECG processor with difference-insensitive QRS detection and lossless compression. IEICE Electron. Express 14(12): 20170524 (2017) - [j11]Jiahui Luo, Zhijian Chen, Xiaoyan Xiang, Jianyi Meng:
A lifting wavelet based lossless and lossy ECG compression processor for wireless sensors. IEICE Electron. Express 14(20): 20170865 (2017) - [j10]Yin Xu, Zhijian Chen, Xiaoyan Xiang, Jianyi Meng:
A granular resampling method based energy-efficient architecture for heartbeat classification in ECG. IEICE Electron. Express 14(22): 20170984 (2017) - [j9]Zhan-Hui Li, Tao-Tao Zhu, Zhi-Jian Chen, Jian-Yi Meng, Xiaoyan Xiang, Xiaolang Yan:
Eliminating Timing Errors Through Collaborative Design to Maximize the Throughput. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 670-682 (2017) - [j8]Tao-Tao Zhu, Jian-Yi Meng, Xiaoyan Xiang, Xiaolang Yan:
Error-Resilient Integrated Clock Gate for Clock-Tree Power Optimization on a Wide Voltage IOT Processor. IEEE Trans. Very Large Scale Integr. Syst. 25(5): 1681-1693 (2017) - [j7]Sheng Wang, Chen Chen, Xiaoyan Xiang, Jian-Yi Meng:
A Variation-Tolerant Near-Threshold Processor With Instruction-Level Error Correction. IEEE Trans. Very Large Scale Integr. Syst. 25(7): 1993-2006 (2017) - [j6]Zhenqiang Yong, Xiaoyan Xiang, Chen Chen, Jianyi Meng:
An Energy-Efficient and Wide-Range Voltage Level Shifter With Dual Current Mirror. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3534-3538 (2017) - 2016
- [j5]Jing Qiu, Xiaoyan Xiang, Zhijian Chen, Jianyi Meng, Yong Ding:
Ultralow power processor employing block instruction for ECG applications. IEICE Electron. Express 13(2): 20150493 (2016) - [j4]Weiwei Shan, Wentao Dai, Youhua Shi, Peng Cao, Xiaoyan Xiang:
Timing monitoring paths selection for wide voltage IC. IEICE Electron. Express 13(8): 20160095 (2016) - [j3]Li Zhanhui, Yong Ding, Xiaolang Yan, Jianyi Meng, Xiaoyan Xiang:
Light-weight one-cycle timing error correction based on hardware software co-design. IEICE Electron. Express 13(11): 20160411 (2016) - [j2]Ziyi Hao, Xiaoyan Xiang, Chen Chen, Jianyi Meng, Yong Ding, Xiaolang Yan:
EDSU: Error detection and sampling unified flip-flop with ultra-low overhead. IEICE Electron. Express 13(16): 20160682 (2016) - [j1]Zhenqiang Yong, Xiaoyan Xiang, Jianyi Meng, Chen Chen:
TBCT: Time-Borrowing and Clock Token based error correction and its application in microprocessor. IEICE Electron. Express 13(20): 20160766 (2016)
Conference and Workshop Papers
- 2020
- [c11]Chen Chen, Xiaoyan Xiang, Chang Liu, Yunhai Shang, Ren Guo, Dongqi Liu, Yimin Lu, Ziyi Hao, Jiahui Luo, Zhijian Chen, Chunqiang Li, Yu Pu, Jianyi Meng, Xiaolang Yan, Yuan Xie, Xiaoning Qi:
Xuantie-910: Innovating Cloud and Edge Computing by RISC-V. Hot Chips Symposium 2020: 1-19 - [c10]Chen Chen, Xiaoyan Xiang, Chang Liu, Yunhai Shang, Ren Guo, Dongqi Liu, Yimin Lu, Ziyi Hao, Jiahui Luo, Zhijian Chen, Chunqiang Li, Yu Pu, Jianyi Meng, Xiaolang Yan, Yuan Xie, Xiaoning Qi:
Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product. ISCA 2020: 52-64 - 2017
- [c9]Zhenqiang Yong, Xiaoyan Xiang, Chen Chen, Jianyi Meng:
A new error masking flip-flop with one cycle correction penalty. ASICON 2017: 72-75 - [c8]Xiaopei Chen, Sheng Wang, Xiaoyan Xiang, Chen Chen, Jianyi Meng:
A light-weight energy-efficient resilient circuit for variation tolerance. ASICON 2017: 815-818 - 2015
- [c7]Ziyi Hao, Xiaoyan Xiang, Chen Chen, Jianyi Meng:
A timing failure tolerance design with in-field simultaneous error detection and correction. ASICON 2015: 1-4 - [c6]Sheng Wang, Xiaoyan Xiang, Chen Chen, Jianyi Meng:
An energy-efficient microprocessor using multilevel error correction for timing error tolerance. ASICON 2015: 1-4 - [c5]Tao-Tao Zhu, Xiaoyan Xiang, Chen Chen, Jianyi Meng:
A near threshold error resilient processor based on dynamic timing error prediction and within-a-cycle timing error correction. ASICON 2015: 1-4 - 2011
- [c4]Shaolei Feng, Xiaoyan Xiang, Shaohua Kevin Zhou, Roee Lazebnik:
Search for the best matching ultrasound frame based on spatial and temporal saliencies. Medical Imaging: Computer-Aided Diagnosis 2011: 79630N - 2009
- [c3]Zhanzhan Liu, Lihua Yue, Peng Wei, Peiquan Jin, Xiaoyan Xiang:
An adaptive block-set based management for large-scale flash memory. SAC 2009: 1621-1625 - 2008
- [c2]Peng Wei, Lihua Yue, Zhanzhan Liu, Xiaoyan Xiang:
Flash memory management based on predicted data expiry-time in embedded real-time systems. SAC 2008: 1477-1481 - [c1]Xiaoyan Xiang, Lihua Yue, Zhanzhan Liu, Peng Wei:
A reliable B-tree implementation over flash memory. SAC 2008: 1487-1491
Coauthor Index
aka: Jianyi Meng
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