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Pouya Hashemi

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2010 – 2019

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2015
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Pouya Hashemi, Takashi Ando, Karthik Balakrishnan, John Bruley, Sebastian U. Engelmann, John A. Ott, Vijay Narayanan, D.-G. Park, Renee T. Mo, Effendi Leobandung:
High-mobility high-Ge-content Si1-xGex-OI PMOS FinFETs with fins formed using 3D germanium condensation with Ge fraction up to x∼ 0.7, scaled EOT∼8.5Å and ∼10nm fin width. VLSIC 2015: 16-
2010
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Pouya Hashemi:
Gate-all-around silicon nanowire complementary metal-oxide-semiconductors: top-down fabrication and transport enhancement techniques. Massachusetts Institute of Technology, Cambridge, MA, USA, 2010

2000 – 2009

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2005
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Ehsanollah Fathi, Ashkan Behnam, Pouya Hashemi, Behzad Esfandyarpour, Morteza Fathipour:
The Influence of the Stacked and Double Material Gate Structures on the Short Channel Effects in SOI MOSFETS. IEICE Trans. Electron. 88-C(6): 1122-1126 (2005)

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