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ORCIDKai Zhu 0001
Person information
- affiliation: Actel Corporation, Mountain View, CA, USA
- affiliation (former): Q Design Automation, USA
- affiliation (former): Triscend Corp., Mountain View, CA, USA
- affiliation (former): Actel Corporation, Sunnyvale, CA, USA
- affiliation (former): University of Texas, Austin, Department of Computer Sciences, TX, USA
Other persons with the same name
- Kai Zhu — disambiguation page
- Kai Zhu 0002 — Arizona State University, School of Electrical, Computer and Energy Engineering, Tempe, AZ, USA
- Kai Zhu 0003
![[0000-0003-1954-0085]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0003-1954-0085")
— McGill University, Montreal, QC, Canada (and 1 more) - Kai Zhu 0004 — University of Science and Technology of China, Hefei, China
- Kai Zhu 0005 — Jiangsu University of Technology, School of Automobile and Traffic Engineering, Changzhou, China
- Kai Zhu 0006 — University of California at Santa Cruz, Department of Environmental Studies, CA, USA (and 1 more)
- Kai Zhu 0007 — Jiangxi Normal University, College of Science and Technology, Nanchang, China
- Kai Zhu 0008 — Qingdao University of Technology, School of Information and Control Engineering, China (and 1 more)
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2000 – 2009
- 2007
[c9]Kai Zhu:
Post-route LUT output polarity selection for timing optimization. FPGA 2007: 89-96- 2003
- [j5]Yao-Wen Chang, Kai Zhu, Guang-Ming Wu, D. F. Wong, C. K. Wong:
Analysis of FPGA/FPIC switch modules. ACM Trans. Design Autom. Electr. Syst. 8(1): 11-37 (2003) - 2000
- [j4]Yao-Wen Chang, Kai Zhu, D. F. Wong:
Timing-driven routing for symmetrical array-based FPGAs. ACM Trans. Design Autom. Electr. Syst. 5(3): 433-450 (2000) - [j3]Huiqun Liu, Kai Zhu, D. F. Wong:
FPGA Partitioning with Complex Resource Constraints. VLSI Design 11(3): 219-235 (2000)
1990 – 1999
- 1998
- [j2]Kai Zhu, Martin D. F. Wong:
Switch bound allocation for maximizing routability in timing-driven routing of FPGA's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(4): 316-323 (1998) - [c8]Huiqun Liu, Kai Zhu, D. F. Wong:
Circuit Partitioning with Complex Resource Constraints in FPGAs. FPGA 1998: 77-84 - [c7]Kai Zhu, Yao-Wen Chang, D. F. Wong:
Timing-driven routing for symmetrical-array-based FPGAs. ICCD 1998: 628-633 - 1997
- [j1]Kai Zhu, Martin D. F. Wong:
Clock skew minimization during FPGA placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(4): 376-385 (1997) - 1994
- [c6]Kai Zhu, D. F. Wong:
Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs. DAC 1994: 165-170 - [c5]Kai Zhu, D. F. Wong:
Clock Skew Minimization During FPGA Placement. DAC 1994: 232-237 - [c4]Yao-Wen Chang, Shashidhar Thakur, Kai Zhu, D. F. Wong:
A new global routing algorithm for FPGAs. ICCAD 1994: 356-361 - 1993
- [c3]Kai Zhu, D. F. Wong:
Fast Boolean matching for field-programmable gate arrays. EURO-DAC 1993: 352-357 - [c2]Kai Zhu, D. F. Wong, Yao-Wen Chang:
Switch module design with application to two-dimensional segmentation design. ICCAD 1993: 480-485 - 1992
- [c1]Kai Zhu, D. F. Wong:
On channel segmentation design for row-based FPGAs. ICCAD 1992: 26-29
Coauthor Index
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