default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDYao-Wen Chang
Person information
- affiliation: National Taiwan University, Taipei, Taiwan
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
[j116]Ziran Zhu
, Yangjie Mei, Kangkang Deng, Huan He, Jianli Chen, Jun Yang, Yao-Wen Chang:
High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(3): 956-969 (2024)- [j115]Ziran Zhu, Yilin Li, Miaodi Su, Shu Zhang, Haiyuan Su, Yifeng Xiao, Huan He, Jianli Chen, Yao-Wen Chang:
Subgraph matching-based reference placement for printed circuit board designs. J. Supercomput. 80(16): 24324-24357 (2024) - [c255]Zhifeng Lin, Min Wei, Yilu Chen, Peng Zou, Jianli Chen, Yao-Wen Chang:
Electrostatics-Based Analytical Global Placement for Timing Optimization. DATE 2024: 1-6 - [c254]Yao-Wen Chang:
Physical Design Challenges in Modern Heterogeneous Integration. ISPD 2024: 125-134 - [c253]Wei-Hsiang Tseng, Yao-Wen Chang, Jie-Hong Roland Jiang:
Satisfiability Modulo Theories-Based Qubit Mapping for Trapped-Ion Quantum Computing Systems. ISPD 2024: 245-253 - 2023
- [j114]Yao-Wen Chang, Yi-Hsuan Lai:
What attracts young talent from Taiwan to start businesses in mainland China? A fuzzy analytic hierarchy process study. Technol. Anal. Strateg. Manag. 35(4): 394-408 (2023) - [j113]Ping-Wei Huang, Yao-Wen Chang:
Routability-driven Power/Ground Network Optimization Based on Machine Learning. ACM Trans. Design Autom. Electr. Syst. 28(4): 53:1-53:27 (2023) - [j112]Min Wei, Xingyu Tong, Yuan Wen, Jianli Chen, Jun Yu, Wenxing Zhu, Yao-Wen Chang:
Analytical Placement with 3D Poisson's Equation and ADMM-based Optimization for Large-scale 2.5D Heterogeneous FPGAs. ACM Trans. Design Autom. Electr. Syst. 28(5): 70:1-70:24 (2023) - [c252]Zhijie Cai, Peng Zou, Zhengtao Wu, Xingyu Tong, Jun Yu, Jianli Chen, Yao-Wen Chang:
PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy Exploration. DAC 2023: 1-6 - [c251]Wei-Hsu Chen, Yao-Wen Chang:
Graph-Based Simultaneous Placement and Routing for Two-Dimensional Directed Self-Assembly Technology. DAC 2023: 1-6 - [c250]Kuan-Cheng Chen, Yan-Lin Chen, Yu-Sheng Lu, Yao-Wen Chang:
Toward Parallelism-Optimal Topology Generation for Wavelength-Routed Optical NoC Designs. DAC 2023: 1-6 - [c249]Yan-Jen Chen, Yan-Syuan Chen, Wei-Che Tseng, Cheng-Yu Chiang, Yu-Hsiang Lo, Yao-Wen Chang:
Late Breaking Results: Analytical Placement for 3D ICs with Multiple Manufacturing Technologies. DAC 2023: 1-2 - [c248]Min-Hsuan Chung, Je-Wei Chuang, Yao-Wen Chang:
Any-Angle Routing for Redistribution Layers in 2.5D IC Packages. DAC 2023: 1-6 - [c247]Qinghai Liu, Disi Lin, Chuandong Chen, Huan He, Jianli Chen, Yao-Wen Chang:
A Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints. DAC 2023: 1-6 - [c246]Qinghai Liu, Qinfei Tang, Jiarui Chen, Chuandong Chen, Ziran Zhu, Huan He, Jianli Chen, Yao-Wen Chang:
Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints. DAC 2023: 1-6 - [c245]Wei-Hsiang Tseng, Yao-Wen Chang:
Late Breaking Results: An Efficient Bridge-based Compression Algorithm for Topologically Quantum Error Corrected Circuits. DAC 2023: 1-2 - [c244]Yan-Lin Chen, Wei-Che Tseng, Wei-Yao Kao, Yao-Wen Chang:
A General Wavelength-Routed Optical Networks-on-Chip Model with Applications to Provably Good Customized and Fault-Tolerant Topology Designs. ICCAD 2023: 1-7 - [c243]Chung-Chia Lee, Yao-Wen Chang:
Floorplanning for Embedded Multi-Die Interconnect Bridge Packages. ICCAD 2023: 1-8 - [c242]Jhih-Wei Hsu, Kuan-Cheng Chen, Yan-Syuan Chen, Yu-Hsiang Lo, Yao-Wen Chang:
Security-aware Physical Design against Trojan Insertion, Frontside Probing, and Fault Injection Attacks. ISPD 2023: 220-228 - [i2]Wenxing Zhu, Zhipeng Huang, Jianli Chen, Yao-Wen Chang:
Analytical Solution of Poisson's Equation with Application to VLSI Global Placement. CoRR abs/2307.12041 (2023) - 2022
- [j111]Jianli Chen, Ziran Zhu, Longkun Guo, Yu-Wei Tseng, Yao-Wen Chang:
Mixed-Cell-Height Placement With Drain-to-Drain Abutment and Region Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 1103-1115 (2022) - [j110]Yu-Sheng Lu, Yan-Lin Chen, Sheng-Jung Yu, Yao-Wen Chang:
Topological Structure and Physical Layout Co-Design for Wavelength-Routed Optical Networks-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2237-2249 (2022) - [j109]Xiqiong Bai, Ziran Zhu, Pingping Li, Jianli Chen, Tingshen Lan, Xingquan Li, Jun Yu, Wenxing Zhu, Yao-Wen Chang:
Timing-Aware Fill Insertions With Design-Rule and Density Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3529-3542 (2022) - [j108]Jianli Chen, Zhifeng Lin, Yanyue Xie, Wenxing Zhu, Yao-Wen Chang:
Mixed-Cell-Height Placement With Complex Minimum-Implant-Area Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4639-4652 (2022) - [j107]Yu-Sheng Lu, Sheng-Jung Yu, Yao-Wen Chang:
On-Chip Optical Routing With Provably Good Algorithms for Path Clustering and Assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4653-4666 (2022) - [j106]Jianli Chen, Zhipeng Huang, Ziran Zhu, Zheng Peng, Wenxing Zhu, Yao-Wen Chang:
Novel Proximal Group ADMM for Placement Considering Fogging and Proximity Effects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5541-5553 (2022) - [j105]Hsiang-Ting Wen, Yu-Jie Cai, Yang Hsu, Yao-Wen Chang:
Via-Based Redistribution Layer Routing for InFO Packages With Irregular Pad Structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5554-5567 (2022) - [j104]Wei-Hsiang Tseng, Chen-Hao Hsu, Wan-Hsuan Lin, Yao-Wen Chang:
A Bridge-Based Compression Algorithm for Topological Quantum Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5582-5595 (2022) - [c241]Xiqiong Bai, Ziran Zhu, Peng Zou, Jianli Chen, Jun Yu, Yao-Wen Chang:
Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification. ASP-DAC 2022: 172-177 - [c240]Miaodi Su, Hongzhi Ding, Shaohong Weng, Changzhong Zou, Zhonghua Zhou, Yilu Chen, Jianli Chen, Yao-Wen Chang:
High-Correlation 3D Routability Estimation for Congestion-guided Global Routing. ASP-DAC 2022: 580-585 - [c239]Wei-Hsiang Tseng, Yao-Wen Chang:
A bridge-based algorithm for simultaneous primal and dual defects compression on topologically quantum-error-corrected circuits. DAC 2022: 535-540 - [c238]Huimin Wang, Xingyu Tong, Chenyue Ma, Runming Shi, Jianli Chen, Kun Wang, Jun Yu, Yao-Wen Chang:
CNN-inspired analytical global placement for large-scale heterogeneous FPGAs. DAC 2022: 637-642 - [c237]Ziran Zhu, Yangjie Mei, Zijun Li, Jingwen Lin, Jianli Chen, Jun Yang, Yao-Wen Chang:
High-performance placement for large-scale heterogeneous FPGAs with clock constraints. DAC 2022: 643-648 - [c236]Szu-Ru Nie, Yen-Ting Chen, Yao-Wen Chang:
Y-architecture-based flip-chip routing with dynamic programming-based bend minimization. DAC 2022: 955-960 - [c235]Yu-Sheng Lu, Kuan-Cheng Chen, Yu-Ling Hsu, Yao-Wen Chang:
Thermal-aware optical-electrical routing codesign for on-chip signal communications. DAC 2022: 1279-1284 - [c234]Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen:
Flexible chip placement via reinforcement learning: late breaking results. DAC 2022: 1392-1393 - [c233]Miaodi Su, Yifeng Xiao, Shu Zhang, Haiyuan Su, Jiacen Xu, Huan He, Ziran Zhu, Jianli Chen, Yao-Wen Chang:
Subgraph matching based reference placement for PCB designs: late breaking results. DAC 2022: 1400-1401 - [c232]Yang Hsu, Min-Hsuan Chung, Yao-Wen Chang, Ci-Hong Lin:
Transitive Closure Graph-Based Warpage-Aware Floorplanning for Package Designs. ICCAD 2022: 16:1-16:7 - [c231]Yen-Ting Chen, Yao-Wen Chang:
Obstacle-Avoiding Multiple Redistribution Layer Routing with Irregular Structures. ICCAD 2022: 65:1-65:6 - [c230]Cheng-Yuan Wang, Yao-Wen Chang, Yuan-Hao Chang:
SGIRR: Sparse Graph Index Remapping for ReRAM Crossbar Operation Unit and Power Optimization. ICCAD 2022: 165:1-165:7 - [c229]Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Charlie Chung-Ping Chen:
Intelligent Design Automation for Heterogeneous Integration. ISPD 2022: 105-106 - [i1]Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen:
Flexible Multiple-Objective Reinforcement Learning for Chip Placement. CoRR abs/2204.06407 (2022) - 2021
- [j103]Chen-Hao Hsu, Shao-Chun Hung, Hao Chen, Fan-Keng Sun, Yao-Wen Chang:
A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(3): 533-546 (2021) - [j102]Jianli Chen, Yao-Wen Chang, Yu-Chen Huang:
Analytical Placement Considering the Electron-Beam Fogging Effect. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(3): 560-573 (2021) - [j101]Jianli Chen, Yao-Wen Chang, Yen-Yi Wu:
Mixed-Cell-Height Detailed Placement Considering Complex Minimum-Implant-Area Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 2128-2141 (2021) - [j100]Jianli Chen, Ziran Zhu, Wenxing Zhu, Yao-Wen Chang:
A Robust Modulus-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization. ACM Trans. Design Autom. Electr. Syst. 26(2): 15:1-15:28 (2021) - [c228]Bingshu Wang, Lanfan Jiang, Wenxing Zhu, Longkun Guo, Jianli Chen, Yao-Wen Chang:
Two-Stage Neural Network Classifier for the Data Imbalance Problem with Application to Hotspot Detection. DAC 2021: 175-180 - [c227]Chen-Hao Hsu, Wan-Hsuan Lin, Wei-Hsiang Tseng, Yao-Wen Chang:
A Bridge-based Compression Algorithm for Topological Quantum Circuits. DAC 2021: 457-462 - [c226]Yun Chou, Jhih-Wei Hsu, Yao-Wen Chang, Tung-Chieh Chen:
VLSI Structure-aware Placement for Convolutional Neural Network Accelerator Units. DAC 2021: 1117-1122 - [c225]Ming-Hung Chen, Yao-Wen Chang, Jun-Jie Wang:
Performance-Driven Simultaneous Partitioning and Routing for Multi-FPGA Systems. DAC 2021: 1129-1134 - [c224]Yu-Jie Cai, Yang Hsu, Yao-Wen Chang:
Simultaneous Pre- and Free-assignment Routing for Multiple Redistribution Layers with Irregular Vias. DAC 2021: 1147-1152 - [c223]Zhifeng Lin, Yanyue Xie, Gang Qian, Jianli Chen, Sifei Wang, Jun Yu, Yao-Wen Chang:
Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints. DATE 2021: 1564-1569 - [c222]Fu-Yu Chuang, Yao-Wen Chang:
On-chip Optical Routing with Waveguide Matching Constraints. ICCAD 2021: 1-6 - [c221]Zih-Yao Lin, Yao-Wen Chang:
A Row-Based Algorithm for Non-Integer Multiple-Cell-Height Placement. ICCAD 2021: 1-6 - [c220]Wei-Kai Liu, Ming-Hung Chen, Chia-Ming Chang, Chen-Chia Chang, Yao-Wen Chang:
Time-Division Multiplexing Based System-Level FPGA Routing. ICCAD 2021: 1-6 - [c219]Cheng-Ying Hsieh, Yao-Wen Chang, Chien Chen, Jyh-Cheng Chen:
Design and implementation of a generic 5G user plane function development framework. MobiCom 2021: 846-848 - [c218]Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen:
Opportunities for 2.5/3D Heterogeneous SoC Integration. VLSI-DAT 2021: 1 - 2020
- [j99]Jianli Chen, Zhifeng Lin, Yun-Chih Kuo, Chau-Chin Huang, Yao-Wen Chang, Shih-Chun Chen, Chun-Han Chiang, Sy-Yen Kuo:
Clock-Aware Placement for Large-Scale Heterogeneous FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5042-5055 (2020) - [j98]Ziran Zhu, Jianli Chen, Wenxing Zhu, Yao-Wen Chang:
Mixed-Cell-Height Legalization Considering Technology and Region Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5128-5141 (2020) - [c217]Chun-Han Chiang, Fu-Yu Chuang, Yao-Wen Chang:
Unified Redistribution Layer Routing for 2.5D IC Packages. ASP-DAC 2020: 331-337 - [c216]Jianli Chen, Zhipeng Huang, Ye Huang, Wenxing Zhu, Jun Yu, Yao-Wen Chang:
An Efficient EPIST Algorithm for Global Placement with Non-Integer Multiple-Height Cells *. DAC 2020: 1-6 - [c215]Jianli Chen, Ziran Zhu, Qinghai Liu, Yimin Zhang, Wenxing Zhu, Yao-Wen Chang:
Hamiltonian Path Based Mixed-Cell-Height Legalization for Neighbor Diffusion Effect Mitigation. DAC 2020: 1-6 - [c214]Chau-Chin Huang, Gustavo E. Téllez, Gi-Joon Nam, Yao-Wen Chang:
Latch Clustering for Timing-Power Co-Optimization. DAC 2020: 1-6 - [c213]Yu-Sheng Lu, Sheng-Jung Yu, Yao-Wen Chang:
Topological Structure and Physical Layout Codesign for Wavelength-Routed Optical Networks-on-Chip. DAC 2020: 1-6 - [c212]Yu-Sheng Lu, Sheng-Jung Yu, Yao-Wen Chang:
A Provably Good Wavelength-Division-Multiplexing-Aware Clustering Algorithm for On-Chip Optical Routing. DAC 2020: 1-6 - [c211]Hsiang-Ting Wen, Yu-Jie Cai, Yang Hsu, Yao-Wen Chang:
Via-based Redistribution Layer Routing for InFO Packages with Irregular Pad Structures. DAC 2020: 1-6 - [c210]Peng Zou, Zhifeng Lin, Xiao Shi, Yingjie Wu, Jianli Chen, Jun Yu, Yao-Wen Chang:
Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification. DAC 2020: 1-6 - [c209]Run-Yi Wang, Yao-Wen Chang:
Routability-Aware Pin Access Optimization for Monolithic 3D Designs. ICCAD 2020: 2:1-2:6 - [c208]Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen:
Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration. ICCAD 2020: 125:1-125:7 - [c207]Chieh Roger Lo, Teng-Hao Yeh, Wei-Chen Chen, Hang-Ting Lue, Keh-Chung Wang, Chih-Yuan Lu, Yao-Wen Chang, Yung-Hsiang Chen, Chu-Yung Liu:
Study of the Walk-Out Effect of Junction Breakdown Instability of the High-Voltage Depletion-Mode N-Channel MOSFET for NAND Flash Peripheral Device and an Efficient Layout Solution. IRPS 2020: 1-6
2010 – 2019
- 2019
- [j97]Dar-Ren Chen, Yao-Wen Chang, Hwa-Koon Wu, Wei-Chung Shia, Yu-Len Huang:
Multiview Contouring for Breast Tumor on Magnetic Resonance Imaging. J. Digit. Imaging 32(5): 713-727 (2019) - [j96]Yu-Hsuan Su, Yao-Wen Chang:
DSA-Compliant Routing for 2-D Patterns Using Block Copolymer Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 267-280 (2019) - [j95]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [c206]Yen-Chun Liu, Tung-Chieh Chen, Yao-Wen Chang, Sy-Yen Kuo:
MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs. ASP-DAC 2019: 557-562 - [c205]Fan-Keng Sun, Yao-Wen Chang:
BiG: A Bivariate Gradient-Based Wirelength Model for Analytical Circuit Placement. DAC 2019: 118 - [c204]Chen-Hao Hsu, Shao-Chun Hung, Hao Chen, Fan-Keng Sun, Yao-Wen Chang:
A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing. DAC 2019: 217 - [c203]Yu-Hsuan Chang, Hsiang-Ting Wen, Yao-Wen Chang:
Obstacle-Aware Group-Based Length-Matching Routing for Pre-Assignment Area-I/O Flip-Chip Designs. ICCAD 2019: 1-8 - [c202]Jianli Chen, Wenxing Zhu, Jun Yu, Lei He, Yao-Wen Chang:
Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5D Heterogeneous FPGAs. ICCAD 2019: 1-8 - [c201]Tingshen Lan, Xingquan Li, Jianli Chen, Jun Yu, Lei He, Senhua Dong, Wenxing Zhu, Yao-Wen Chang:
Timing-Aware Fill Insertions with Design-Rule and Density Constraints. ICCAD 2019: 1-8 - [c200]Zhan-Ling Wang, Yao-Wen Chang:
Graph- and ILP-Based Cut Redistribution for Two-Dimensional Directed Self-Assembly. ICCAD 2019: 1-7 - [c199]Xingquan Li, Jianli Chen, Wenxing Zhu, Yao-Wen Chang:
Analytical Mixed-Cell-Height Legalization Considering Average and Maximum Movement Minimization. ISPD 2019: 27-34 - 2018
- [j94]Chau-Chin Huang, Hsin-Ying Lee, Bo-Qiao Lin, Sheng-Wei Yang, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang, Tung-Chieh Chen, Ismail Bustany:
NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(3): 669-681 (2018) - [j93]Zhi-Wen Lin, Shao-Yun Fang, Yao-Wen Chang, Wei-Cheng Rao, Chieh-Hsiung Kuan:
Provably Good Max-Min-m-Neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication. IEEE Trans. Very Large Scale Integr. Syst. 26(2): 378-391 (2018) - [c198]Yu-Sheng Lu, Yu-Hsuan Chang, Yao-Wen Chang:
WB-trees: a meshed tree representation for FinFET analog layout designs. DAC 2018: 9:1-9:6 - [c197]Run-Yi Wang, Chia-Cheng Pai, Jun-Jie Wang, Hsiang-Ting Wen, Yu-Cheng Pai, Yao-Wen Chang, James Chien-Mo Li, Jie-Hong Roland Jiang:
Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction. DAC 2018: 45:1-45:6 - [c196]Hai-Juan Yu, Yao-Wen Chang:
DSA-friendly detailed routing considering double patterning and DSA template assignments. DAC 2018: 49:1-49:6 - [c195]Ziran Zhu, Jianli Chen, Zheng Peng, Wenxing Zhu, Yao-Wen Chang:
Generalized augmented lagrangian and its applications to VLSI global placement. DAC 2018: 149:1-149:6 - [c194]Wenxing Zhu, Zhipeng Huang, Jianli Chen, Yao-Wen Chang:
Analytical solution of Poisson's equation and its application to VLSI global placement. ICCAD 2018: 2 - [c193]Jianli Chen, Li Yang, Zheng Peng, Wenxing Zhu, Yao-Wen Chang:
Novel proximal group ADMM for placement considering fogging and proximity effects. ICCAD 2018: 3 - [c192]Shih-Chun Chen, Richard Sun, Yao-Wen Chang:
Simultaneous partitioning and signals grouping for time-division multiplexing in 2.5D FPGA-based systems. ICCAD 2018: 4 - [c191]Yu-Wei Tseng, Yao-Wen Chang:
Mixed-cell-height placement considering drain-to-drain abutment. ICCAD 2018: 64 - [c190]Ziran Zhu, Xingquan Li, Yuhang Chen, Jianli Chen, Wenxing Zhu, Yao-Wen Chang:
Mixed-cell-height legalization considering technology and region constraints. ICCAD 2018: 65 - [c189]Jianli Chen, Peng Yang, Xingquan Li, Wenxing Zhu, Yao-Wen Chang:
Mixed-cell-height placement with complex minimum-implant-area constraints. ICCAD 2018: 66 - [c188]Fan-Keng Sun, Hao Chen, Ching-Yu Chen, Chen-Hao Hsu, Yao-Wen Chang:
A multithreaded initial detailed routing algorithm considering global routing guides. ICCAD 2018: 82 - 2017
- [j92]Yao-Wen Chang:
An Interview With Professor Chenming Hu, Father of 3D Transistors. IEEE Des. Test 34(5): 90-96 (2017) - [j91]Yu-Hsuan Su, Yao-Wen Chang:
Nanowire-Aware Routing Considering High Cut Mask Complexity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(6): 964-977 (2017) - [j90]Zhi-Wen Lin, Yao-Wen Chang:
Cut Redistribution With Directed-Self-Assembly Templates for Advanced 1-D Gridded Layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(12): 2066-2079 (2017) - [j89]Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson:
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 1-20 (2017) - [c187]Chao-Hung Wang, Yen-Yi Wu, Jianli Chen, Yao-Wen Chang, Sy-Yen Kuo, Wenxing Zhu, Genghua Fan:
An effective legalization algorithm for mixed-cell-height standard cells. ASP-DAC 2017: 450-455 - [c186]Jianli Chen, Ziran Zhu, Wenxing Zhu, Yao-Wen Chang:
Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs. DAC 2017: 52:1-52:6 - [c185]Yu-Chen Huang, Yao-Wen Chang:
Fogging Effect Aware Placement in Electron Beam Lithography. DAC 2017: 53:1-53:6 - [c184]Chau-Chin Huang, Bo-Qiao Lin, Hsin-Ying Lee, Yao-Wen Chang, Kuo-Sheng Wu, Jun-Zhi Yang:
Graph-Based Logic Bit Slicing for Datapath-Aware Placement. DAC 2017: 71:1-71:6 - [c183]Zhi-Wen Lin, Yao-Wen Chang:
Detailed Placement for Two-Dimensional Directed Self-Assembly Technology. DAC 2017: 79:1-79:6 - [c182]Yen-Yi Wu, Yao-Wen Chang:
Mixed-cell-height detailed placement considering complex minimum-implant-area constraints. ICCAD 2017: 65-72 - [c181]Sheng-Wei Yang, Yao-Wen Chang, Tung-Chieh Chen:
Blockage-aware terminal propagation for placement wirelength minimization. ICCAD 2017: 73-80 - [c180]Szu-To Chen, Yao-Wen Chang, Tung-Chieh Chen:
An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designs. ICCAD 2017: 496-503 - [c179]Chin-Hao Chang, Yao-Wen Chang, Tung-Chieh Chen:
A novel damped-wave framework for macro placement. ICCAD 2017: 504-511 - [c178]Yun-Chih Kuo, Chau-Chin Huang, Shih-Chun Chen, Chun-Han Chiang, Yao-Wen Chang, Sy-Yen Kuo:
Clock-aware placement for large-scale heterogeneous FPGAs. ICCAD 2017: 519-526 - [c177]Ting-Chou Lin, Chia-Chih Chi, Yao-Wen Chang:
Redistribution layer routing for wafer-level integrated fan-out package-on-packages. ICCAD 2017: 561-568 - [c176]Shih-Chun Chen, Yao-Wen Chang:
FPGA placement and routing. ICCAD 2017: 914-921 - [c175]Yao-Wen Chang:
Generalized Force Directed Relaxation with Optimal Regions and Its Applications to Circuit Placement. ISPD 2017: 115-120 - 2016
- [j88]Hui-Ju Katherine Chiang, Chi-Yuan Liu, Jie-Hong R. Jiang, Yao-Wen Chang:
Simultaneous EUV Flare Variation Minimization and CMP Control by Coupling-Aware Dummification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(4): 598-610 (2016) - [j87]Hung-Chih Ou, Kai-Han Tseng, Jhao-Yan Liu, I-Peng Wu, Yao-Wen Chang:
Layout-Dependent Effects-Aware Analytical Analog Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(8): 1243-1254 (2016) - [j86]Yu-Hsuan Su, Yu-Chen Huang, Liang-Chun Tsai, Yao-Wen Chang, Shayak Banerjee:
Fast Lithographic Mask Optimization Considering Process Variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(8): 1345-1357 (2016) - [j85]Iou-Jen Liu, Shao-Yun Fang, Yao-Wen Chang:
Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1519-1531 (2016) - [c174]Zhi-Wen Lin, Yao-Wen Chang:
Cut redistribution with directed self-assembly templates for advanced 1-D gridded layouts. ASP-DAC 2016: 89-94 - [c173]Chien-Hsiung Chiou, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang:
Circular-contour-based obstacle-aware macro placement. ASP-DAC 2016: 172-177 - [c172]Mark Po-Hung Lin, Yao-Wen Chang, Chih-Ming Hung:
Recent research development and new challenges in analog layout synthesis. ASP-DAC 2016: 617-622 - [c171]I-Peng Wu, Hung-Chih Ou, Yao-Wen Chang:
QB-trees: towards an optimal topological representation and its applications to analog layout designs. DAC 2016: 80:1-80:6 - [c170]Chau-Chin Huang, Yen-Chun Liu, Yu-Sheng Lu, Yun-Chih Kuo, Yao-Wen Chang, Sy-Yen Kuo:
Timing-driven cell placement optimization for early slack histogram compression. DAC 2016: 81:1-81:6 - [c169]Kai-Han Tseng, Yao-Wen Chang, Charles C. C. Liu:
Minimum-implant-area-aware detailed placement with spacing constraints. DAC 2016: 84:1-84:6 - [c168]Bo-Qiao Lin, Ting-Chou Lin, Yao-Wen Chang:
Redistribution layer routing for integrated fan-out wafer-level chip-scale packages. ICCAD 2016: 23 - [c167]Yu-Hsuan Su, Yao-Wen Chang:
VCR: simultaneous via-template and cut-template-aware routing for directed self-assembly technology. ICCAD 2016: 49 - [c166]Yu-Hsuan Su, Yao-Wen Chang:
DSA-compliant routing for two-dimensional patterns using block copolymer lithography. ICCAD 2016: 50 - [c165]Zhi-Wen Lin, Yao-Wen Chang:
Double-Patterning Aware DSA Template Guided Cut Redistribution for Advanced 1-D Gridded Designs. ISPD 2016: 47-54 - 2015
- [j84]Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang, Hui-Fang Tsao:
Coupling-Aware Length-Ratio-Matching Routing for Capacitor Arrays in Analog Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(2): 161-172 (2015) - [j83]Iou-Jen Liu, Shao-Yun Fang, Yao-Wen Chang:
Stitch-Aware Routing for Multiple E-Beam Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(3): 471-482 (2015) - [c164]Chau-Chin Huang, Chien-Hsiung Chiou, Kai-Han Tseng, Yao-Wen Chang:
Detailed-Routing-Driven analytical standard-cell placement. ASP-DAC 2015: 378-383 - [c163]Po-Ya Hsu, Yao-Wen Chang:
Non-stitch triple patterning-aware routing based on conflict graph pre-coloring. ASP-DAC 2015: 390-395 - [c162]Shao-Yun Fang, Yi-Shu Tai, Yao-Wen Chang:
Layout decomposition for Spacer-is-Metal (SIM) self-aligned double patterning. ASP-DAC 2015: 671-676 - [c161]Sheng-Yen Chen, Yao-Wen Chang:
Routing-architecture-aware analytical placement for heterogeneous FPGAs. DAC 2015: 27:1-27:6 - [c160]Yu-Hsuan Su, Yao-Wen Chang:
Nanowire-aware routing considering high cut mask complexity. DAC 2015: 138:1-138:6 - [c159]Hung-Chih Ou, Kai-Han Tseng, Jhao-Yan Liu, I-Peng Wu, Yao-Wen Chang:
Layout-dependent-effects-aware analytical analog placement. DAC 2015: 189:1-189:6 - [c158]Hung-Chih Ou, Kai-Han Tseng, Yao-Wen Chang:
Cutting structure-aware analog placement based on self-aligned double patterning with e-beam lithography. DAC 2015: 190:1-190:6 - [c157]Yao-Wen Chang, Ru-Gun Liu, Shao-Yun Fang:
EUV and e-beam manufacturability: challenges and solutions. DAC 2015: 198:1-198:6 - [c156]Zhi-Wen Lin, Shao-Yun Fang, Yao-Wen Chang, Wei-Cheng Rao, Chieh-Hsiung Kuan:
Provably Good Max-Min-m-neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication. ICCAD 2015: 388-395 - [c155]Chau-Chin Huang, Hsin-Ying Lee, Bo-Qiao Lin, Sheng-Wei Yang, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang:
Detailed-Routability-Driven Analytical Placement for Mixed-Size Designs with Technology and Region Constraints. ICCAD 2015: 508-513 - 2014
- [j82]Yuan-Kai Ho, Hsu-Chieh Lee, Webber Lee, Yao-Wen Chang, Chen-Feng Chang, I-Jye Lin, Chin-Fang Shen:
Obstacle-Avoiding Free-Assignment Routing for Flip-Chip Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(2): 224-236 (2014) - [j81]Shao-Yun Fang, Yao-Wen Chang, Wei-Yu Chen:
A Novel Layout Decomposition Algorithm for Triple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(3): 397-408 (2014) - [j80]Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Sheng Chou, Tzu-Hen Lin, Tung-Chieh Chen, Yao-Wen Chang:
NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1914-1927 (2014) - [j79]Hung-Chih Ou, Hsing-Chih Chang Chien, Yao-Wen Chang:
Nonuniform Multilevel Analog Routing With Matching Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1942-1954 (2014) - [c154]Iou-Jen Liu, Shao-Yun Fang, Yao-Wen Chang:
Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process. DAC 2014: 50:1-50:6 - [c153]Chi-Yuan Liu, Hui-Ju Katherine Chiang, Yao-Wen Chang, Jie-Hong R. Jiang:
Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification. DAC 2014: 54:1-54:6 - [c152]Yi-Fang Chen, Chau-Chin Huang, Chien-Hsiung Chiou, Yao-Wen Chang, Chang-Jen Wang:
Routability-Driven Blockage-Aware Macro Placement. DAC 2014: 124:1-124:6 - [c151]Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang:
Functional ECO Using Metal-Configurable Gate-Array Spare Cells. DAC 2014: 191:1-191:6 - [c150]Kuan-Hsien Ho, Yao-Wen Chang:
A New Asynchronous Pipeline Template for Power and Performance Optimization. DAC 2014: 204:1-204:6 - [c149]Yu-Hsuan Su, Yu-Chen Huang, Liang-Chun Tsai, Yao-Wen Chang, Shayak Banerjee:
Fast lithographic mask optimization considering process variation. ICCAD 2014: 230-237 - [c148]Yu-Chen Chen, Sheng-Yen Chen, Yao-Wen Chang:
Efficient and effective packing and analytical placement for large-scale heterogeneous FPGAs. ICCAD 2014: 647-654 - [c147]Chi-Yuan Liu, Yao-Wen Chang:
Simultaneous EUV flare- and CMP-aware placement. ICCD 2014: 249-255 - [c146]Yao-Wen Chang, Ruey-Kai Sheu, Syuan-Ru Jhu, Yue-Shan Chang:
Design and Implementation of a RESTful Notification Service. ICS 2014: 1375-1385 - [c145]Chung-Wei Lin, Tzu-Hsuan Hsu, Xin-Wei Shih, Yao-Wen Chang:
Buffered clock tree synthesis considering self-heating effects. ISLPED 2014: 111-116 - [e4]Yao-Wen Chang:
The IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014, San Jose, CA, USA, November 3-6, 2014. IEEE 2014, ISBN 978-1-4799-6277-8 [contents] - 2013
- [j78]Yao-Wen Chang:
Circuit placement challenges: technical perspective. Commun. ACM 56(6): 104 (2013) - [j77]Shao-Yun Fang, Wei-Yu Chen, Yao-Wen Chang:
Graph-Based Subfield Scheduling for Electron-Beam Photomask Fabrication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(2): 189-201 (2013) - [j76]Meng-Kai Hsu, Valeriy Balabanov, Yao-Wen Chang:
TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel Weighted-Average Wirelength Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(4): 497-509 (2013) - [j75]Yuan-Kai Ho, Hsu-Chieh Lee, Yao-Wen Chang:
Escape Routing for Staggered-Pin-Array PCBs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(9): 1347-1356 (2013) - [j74]Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang:
ECO Optimization Using Metal-Configurable Gate-Array Spare Cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(11): 1722-1733 (2013) - [c144]Yuan-Kai Ho, Xin-Wei Shih, Yao-Wen Chang, Chung-Kuan Cheng:
Layer minimization in escape routing for staggered-pin-array PCBs. ASP-DAC 2013: 187-192 - [c143]Xin-Wei Shih, Tzu-Hsuan Hsu, Hsu-Chieh Lee, Yao-Wen Chang, Kai-Yuan Chao:
Symmetrical buffered clock-tree synthesis with supply-voltage alignment. ASP-DAC 2013: 447-452 - [c142]Hsing-Chih Chang Chien, Hung-Chih Ou, Tung-Chieh Chen, Ta-Yu Kuan, Yao-Wen Chang:
Double patterning lithography-aware analog placement. DAC 2013: 4:1-4:6 - [c141]Hung-Chih Ou, Hsing-Chih Chang Chien, Yao-Wen Chang:
Simultaneous analog placement and routing with current flow and current density considerations. DAC 2013: 5:1-5:6 - [c140]Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang, Hui-Fang Tsao:
Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits. DAC 2013: 6:1-6:6 - [c139]Tzu-Hen Lin, Pritha Banerjee, Yao-Wen Chang:
An efficient and effective analytical placer for FPGAs. DAC 2013: 10:1-10:6 - [c138]Shao-Yun Fang, Iou-Jen Liu, Yao-Wen Chang:
Stitch-aware routing for multiple e-beam lithography. DAC 2013: 25:1-25:6 - [c137]Yuan-Kai Ho, Yao-Wen Chang:
Multiple chip planning for chip-interposer codesign. DAC 2013: 27:1-27:6 - [c136]Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Tung-Chieh Chen, Yao-Wen Chang:
Routability-driven placement for hierarchical mixed-size circuit designs. DAC 2013: 151:1-151:6 - [c135]Shao-Yun Fang, Chung-Wei Lin, Guang-Wan Liao, Yao-Wen Chang:
Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling. ISPD 2013: 77-84 - 2012
- [j73]Shao-Yun Fang, Szu-Yu Chen, Yao-Wen Chang:
Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(5): 703-716 (2012) - [j72]Chung-Wei Lin, Po-Wei Lee, Yao-Wen Chang, Chin-Fang Shen, Wei-Chih Tseng:
An Efficient Pre-Assignment Routing Algorithm for Flip-Chip Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(6): 878-889 (2012) - [j71]Meng-Kai Hsu, Yao-Wen Chang:
Unified Analytical Global Placement for Large-Scale Mixed-Size Circuit Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(9): 1366-1378 (2012) - [j70]Xin-Wei Shih, Yao-Wen Chang:
Fast Timing-Model Independent Buffered Clock-Tree Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(9): 1393-1404 (2012) - [j69]Kuan-Hsien Ho, Jie-Hong Roland Jiang, Yao-Wen Chang:
TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(11): 1723-1733 (2012) - [j68]Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang:
Timing ECO Optimization Via Bézier Curve Smoothing and Fixability Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(12): 1857-1866 (2012) - [c134]Hung-Chih Ou, Hsing-Chih Chang Chien, Yao-Wen Chang:
Non-uniform multilevel analog routing with matching constraints. DAC 2012: 549-554 - [c133]Sheng Chou, Meng-Kai Hsu, Yao-Wen Chang:
Structure-aware placement for datapath-intensive circuit designs. DAC 2012: 762-767 - [c132]Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang:
Timing ECO optimization using metal-configurable gate-array spare cells. DAC 2012: 802-807 - [c131]Hsu-Chieh Lee, Yao-Wen Chang:
A chip-package-board co-design methodology. DAC 2012: 1082-1087 - [c130]Po-Wei Lee, Hsu-Chieh Lee, Yuan-Kai Ho, Yao-Wen Chang, Chen-Feng Chang, I-Jye Lin, Chin-Fang Shen:
Obstacle-avoiding free-assignment routing for flip-chip designs. DAC 2012: 1088-1093 - [c129]Shao-Yun Fang, Yao-Wen Chang:
Simultaneous flare level and flare variation minimization with dummification in EUVL. DAC 2012: 1179-1184 - [c128]Shao-Yun Fang, Yao-Wen Chang, Wei-Yu Chen:
A novel layout decomposition algorithm for triple patterning lithography. DAC 2012: 1185-1190 - [c127]Da-Cheng Juan, Yi-Lin Chuang, Diana Marculescu, Yao-Wen Chang:
Statistical thermal modeling and optimization considering leakage power variations. DATE 2012: 605-610 - [c126]Shao-Yun Fang, Wei-Yu Chen, Yao-Wen Chang:
Graph-based subfield scheduling for electron-beam photomask fabrication. ISPD 2012: 9-16 - 2011
- [j67]Prashant Saxena, Yao-Wen Chang:
Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 165-166 (2011) - [j66]Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif:
Simultaneous Layout Migration and Decomposition for Double Patterning Technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 284-294 (2011) - [j65]Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang:
Thermal-Driven Analog Placement Considering Device Matching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 325-336 (2011) - [j64]Cliff Chiung-Yu Lin, Yao-Wen Chang:
Cross-Contamination Aware Design Methodology for Pin-Constrained Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(6): 817-828 (2011) - [j63]Yi-Lin Chuang, Po-Wei Lee, Yao-Wen Chang:
Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11): 1649-1662 (2011) - [j62]Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang:
Pulsed-Latch Aware Placement for Timing-Integrity Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(12): 1856-1869 (2011) - [c125]Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang:
Simultaneous functional and timing ECO. DAC 2011: 140-145 - [c124]Meng-Kai Hsu, Yao-Wen Chang, Valeriy Balabanov:
TSV-aware analytical placement for 3D IC designs. DAC 2011: 664-669 - [c123]Meng-Kai Hsu, Sheng Chou, Tzu-Hen Lin, Yao-Wen Chang:
Routability-driven analytical placement for mixed-size circuit designs. ICCAD 2011: 80-84 - [c122]Yi-Lin Chuang, Hong-Ting Lin, Tsung-Yi Ho, Yao-Wen Chang, Diana Marculescu:
PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs. ICCAD 2011: 85-90 - [c121]Yuan-Kai Ho, Hsu-Chieh Lee, Yao-Wen Chang:
Escape routing for staggered-pin-array PCBs. ICCAD 2011: 306-309 - [c120]Hui-Fang Tsao, Pang-Yen Chou, Shih-Lun Huang, Yao-Wen Chang, Mark Po-Hung Lin, Duan-Ping Chen, Dick Liu:
A corner stitching compliant B∗-tree representation and its applications to analog placement. ICCAD 2011: 507-511 - [c119]Pang-Yen Chou, Hung-Chih Ou, Yao-Wen Chang:
Heterogeneous B∗-trees for analog placement with symmetry and regularity considerations. ICCAD 2011: 512-516 - [c118]Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang:
Timing ECO optimization via Bézier curve smoothing and fixability identification. ICCAD 2011: 742-746 - [c117]Ping-Hung Yuh, Cliff Chiung-Yu Lin, Tsung-Wei Huang, Tsung-Yi Ho, Chia-Lin Yang, Yao-Wen Chang:
A SAT-based routing algorithm for cross-referencing biochips. SLIP 2011: 1-7 - [e3]Yao-Wen Chang, Jiang Hu:
Proceedings of the 2011 International Symposium on Physical Design, ISPD 2011, Santa Barbara, California, USA, March 27-30, 2011. ACM 2011, ISBN 978-1-4503-0550-1 [contents] - 2010
- [j61]Jaw-Luen Tang, Yao-Wen Chang:
Design of an Omnidirectional Multibeam Transmitter for High-Speed Indoor Wireless Communications. EURASIP J. Wirel. Commun. Netw. 2010 (2010) - [j60]Tai-Chen Chen, Guang-Wan Liao, Yao-Wen Chang:
Predictive Formulae for OPC With Applications to Lithography-Friendly Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(1): 40-50 (2010) - [j59]Chin-Hsiung Hsu, Huang-Yu Chen, Yao-Wen Chang:
Multilayer Global Routing With Via and Wire Capacity Considerations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 685-696 (2010) - [j58]Kuan-Hsien Ho, Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang:
ECO Timing Optimization Using Spare Cells and Technology Remapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 697-710 (2010) - [j57]Jia-Wei Fang, Yao-Wen Chang:
Area-I/O Flip-Chip Routing for Chip-Package Co-Design Considering Signal Skews. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 711-721 (2010) - [j56]Cliff Chiung-Yu Lin, Yao-Wen Chang:
ILP-Based Pin-Count Aware Design Methodology for Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(9): 1315-1327 (2010) - [c116]Paul Falkenstern, Yuan Xie, Yao-Wen Chang, Yu Wang:
Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis. ASP-DAC 2010: 169-174 - [c115]Kuan-Hsien Ho, Jie-Hong R. Jiang, Yao-Wen Chang:
TRECO: dynamic technology remapping for timing engineering change orders. ASP-DAC 2010: 331-336 - [c114]Xin-Wei Shih, Chung-Chun Cheng, Yuan-Kai Ho, Yao-Wen Chang:
Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization. ASP-DAC 2010: 395-400 - [c113]Xin-Wei Shih, Yao-Wen Chang:
Fast timing-model independent buffered clock-tree synthesis. DAC 2010: 80-85 - [c112]Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang:
Pulsed-latch aware placement for timing-integrity optimization. DAC 2010: 280-285 - [c111]Cliff Chiung-Yu Lin, Yao-Wen Chang:
Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips. DAC 2010: 641-646 - [c110]Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif:
Template-mask design methodology for double patterning technology. ICCAD 2010: 107-111 - [c109]Shao-Yun Fang, Tzuo-Fan Chien, Yao-Wen Chang:
Redundant-wires-aware ECO timing and mask cost optimization. ICCAD 2010: 381-386 - [c108]Hsu-Chieh Lee, Yao-Wen Chang, Po-Wei Lee:
Recent research development in flip-chip routing. ICCAD 2010: 404-410 - [c107]Xin-Wei Shih, Hsu-Chieh Lee, Kuan-Hsien Ho, Yao-Wen Chang:
High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees. ICCAD 2010: 452-457 - [c106]Szu-Yu Chen, Yao-Wen Chang:
Native-conflict-aware wire perturbation for double patterning technology. ICCAD 2010: 556-561 - [c105]Meng-Kai Hsu, Yao-Wen Chang:
Unified analytical global placement for large-scale mixed-size circuit designs. ICCAD 2010: 657-662 - [c104]Yi-Lin Chuang, Gi-Joon Nam, Charles J. Alpert, Yao-Wen Chang, Jarrod A. Roy, Natarajan Viswanathan:
Design-hierarchy aware mixed-size placement for routability optimization. ICCAD 2010: 663-668 - [c103]Shih-Lun Huang, Chung-Wei Lin, Yao-Wen Chang:
Efficient provably good OPC modeling and its applications to interconnect optimization. ICCD 2010: 336-341 - [c102]Huang-Yu Chen, Szu-Jui Chou, Yao-Wen Chang:
Density gradient minimization with coupling-constrained dummy fill for CMP control. ISPD 2010: 105-111 - [e2]Prashant Saxena, Yao-Wen Chang:
Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010. ACM 2010, ISBN 978-1-60558-920-6 [contents]
2000 – 2009
- 2009
- [j55]Yao-Wen Chang, Zhe-Wei Jiang, Tung-Chieh Chen:
Essential Issues in Analytical Placement Algorithms. Inf. Media Technol. 4(4): 815-836 (2009) - [j54]Yao-Wen Chang, Zhe-Wei Jiang, Tung-Chieh Chen:
Essential Issues in Analytical Placement Algorithms. IPSJ Trans. Syst. LSI Des. Methodol. 2: 145-166 (2009) - [j53]Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang:
An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(1): 98-110 (2009) - [j52]Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang:
A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2): 193-206 (2009) - [j51]Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang:
Voltage-Island Partitioning and Floorplanning Under Timing Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5): 690-702 (2009) - [j50]Mark Po-Hung Lin, Yao-Wen Chang, Shyh-Chang Lin:
Analog Placement Based on Symmetry-Island Formulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(6): 791-804 (2009) - [j49]Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang:
A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(9): 1295-1306 (2009) - [j48]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
T-trees: A tree-based representation for temporal and three-dimensional floorplanning. ACM Trans. Design Autom. Electr. Syst. 14(4): 51:1-51:28 (2009) - [c101]Huang-Yu Chen, Chin-Hsiung Hsu, Yao-Wen Chang:
High-performance global routing with fast overflow reduction. ASP-DAC 2009: 582-587 - [c100]Cliff Chiung-Yu Lin, Yao-Wen Chang:
ILP-based pin-count aware design methodology for microfluidic biochips. DAC 2009: 258-263 - [c99]Jia-Wei Fang, Martin D. F. Wong, Yao-Wen Chang:
Flip-chip routing with unified area-I/O pad assignments for package-board co-design. DAC 2009: 336-339 - [c98]Zhe-Wei Jiang, Meng-Kai Hsu, Yao-Wen Chang, Kai-Yuan Chao:
Spare-cell-aware multilevel analytical placement. DAC 2009: 430-435 - [c97]Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang:
Thermal-driven analog placement considering device matching. DAC 2009: 593-598 - [c96]Tzuo-Fan Chien, Wen-Chi Chao, James Chien-Mo Li, Yao-Wen Chang, Kuan-Yu Liao, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng:
BIST design optimization for large-scale embedded memory cores. ICCAD 2009: 197-200 - [c95]Po-Wei Lee, Chung-Wei Lin, Yao-Wen Chang, Chin-Fang Shen, Wei-Chih Tseng:
An efficient pre-assignment routing algorithm for flip-chip designs. ICCAD 2009: 239-244 - [c94]Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif:
Simultaneous layout migration and decomposition for double patterning technology. ICCAD 2009: 595-600 - [c93]Yi-Lin Chuang, Po-Wei Lee, Yao-Wen Chang:
Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs. ICCAD 2009: 666-673 - [c92]Wan-Ping Lee, Diana Marculescu, Yao-Wen Chang:
Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs. ISPD 2009: 5-12 - 2008
- [j47]Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin:
A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2): 286-294 (2008) - [j46]Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang:
Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 643-653 (2008) - [j45]Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang:
Effective Wire Models for X-Architecture Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 654-658 (2008) - [j44]Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han:
Full-Chip Routing Considering Double-Via Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(5): 844-857 (2008) - [j43]Zhe-Wei Jiang, Yao-Wen Chang:
An Optimal Network-Flow-Based Simultaneous Diode and Jumper Insertion Algorithm for Antenna Fixing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(6): 1055-1065 (2008) - [j42]Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang:
NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1228-1240 (2008) - [j41]Chih-Hung Liu, Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Yao-Wen Chang, Sy-Yen Kuo, Shih-Yi Yuan, Yu-Wei Chen:
An Efficient Graph-Based Algorithm for ESD Current Path Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8): 1363-1375 (2008) - [j40]Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Tien-Yueh Liu:
MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1621-1634 (2008) - [j39]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11): 1928-1941 (2008) - [j38]Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Lee, Yao-Wen Chang:
Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11): 2007-2016 (2008) - [j37]Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang:
Metal-Density-Driven Placement for CMP Variation and Routability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2145-2155 (2008) - [c91]Zhe-Wei Jiang, Bor-Yiing Su, Yao-Wen Chang:
Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs. DAC 2008: 167-172 - [c90]Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang:
A progressive-ILP based routing algorithm for cross-referencing biochips. DAC 2008: 284-289 - [c89]Tai-Chen Chen, Guang-Wan Liao, Yao-Wen Chang:
Predictive formulae for OPC with applications to lithography-friendly routing. DAC 2008: 510-515 - [c88]Hsin-Chen Chen, Yi-Lin Chuang, Yao-Wen Chang, Yung-Chung Chang:
Constraint graph-based macro placement for modern mixed-size circuit designs. ICCAD 2008: 218-223 - [c87]Chin-Hsiung Hsu, Huang-Yu Chen, Yao-Wen Chang:
Multi-layer global routing considering via and wire capacities. ICCAD 2008: 350-355 - [c86]Jia-Wei Fang, Kuan-Hsien Ho, Yao-Wen Chang:
Routing for chip-package-board co-design considering differential pairs. ICCAD 2008: 512-517 - [c85]Jia-Wei Fang, Yao-Wen Chang:
Area-I/O flip-chip routing for chip-package co-design. ICCAD 2008: 518-522 - [c84]Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang:
Metal-density driven placement for cmp variation and routability. ISPD 2008: 31-38 - [e1]Tarek A. El-Ghazawi, Yao-Wen Chang, Juinn-Dar Huang, Proshanta Saha:
2008 International Conference on Field-Programmable Technology, FPT 2008, Taipei, Taiwan, December 7-10, 2008. IEEE 2008, ISBN 978-1-4244-2796-3 [contents] - [r2]Tung-Chieh Chen, Yao-Wen Chang:
Packing Floorplan Representations. Handbook of Algorithms for Physical Design Automation 2008 - [r1]Cheng-Kok Koh, Evangeline F. Y. Young, Yao-Wen Chang:
Global Interconnect Planning. Handbook of Algorithms for Physical Design Automation 2008 - 2007
- [b1]Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen:
Full-Chip Nanometer Routing Techniques. Analog Circuits and Signal Processing, Springer 2007, ISBN 978-1-4020-6194-3, pp. I-XI, 1-102 - [j36]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation. ACM J. Emerg. Technol. Comput. Syst. 3(3): 13 (2007) - [j35]Chen-Wei Liu, Yao-Wen Chang:
Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 693-704 (2007) - [j34]Bor-Yiing Su, Yao-Wen Chang, Jiang Hu:
An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 719-733 (2007) - [j33]Tai-Chen Chen, Yao-Wen Chang:
Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6): 1041-1053 (2007) - [j32]Jia-Wei Fang, I-Jye Lin, Yao-Wen Chang, Jyh-Herng Wang:
A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(8): 1417-1429 (2007) - [j31]Hsun-Cheng Lee, Yao-Wen Chang, Hannah Honghua Yang:
MBast-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(8): 1430-1444 (2007) - [j30]Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
Multilevel Full-Chip Routing With Testability and Yield Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1625-1636 (2007) - [j29]Bor-Yiing Su, Yao-Wen Chang:
An Optimal Jumper-Insertion Algorithm for Antenna Avoidance/Fixing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10): 1818-1829 (2007) - [j28]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
Temporal floorplanning using the three-dimensional transitive closure subGraph. ACM Trans. Design Autom. Electr. Syst. 12(4): 37 (2007) - [c83]Chung-Wei Lin, Ming-Chao Tsai, Kuang-Yao Lee, Tai-Chen Chen, Ting-Chi Wang, Yao-Wen Chang:
Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability. ASP-DAC 2007: 238-243 - [c82]Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Denny Liu:
MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. DAC 2007: 447-452 - [c81]Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang:
An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design. DAC 2007: 606-611 - [c80]Hung-Yi Liu, Wan-Ping Lee, Yao-Wen Chang:
A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages. DAC 2007: 887-890 - [c79]I-Jye Lin, Yao-Wen Chang:
An efficient algorithm for statistical circuit optimization using Lagrangian relaxation. ICCAD 2007: 119-124 - [c78]Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Li, Yao-Wen Chang:
Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction. ICCAD 2007: 380-385 - [c77]Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang:
ECO timing optimization using spare cells. ICCAD 2007: 530-535 - [c76]Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang:
An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning. ICCAD 2007: 650-655 - [c75]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
BioRoute: a network-flow based routing algorithm for digital microfluidic biochips. ICCAD 2007: 752-757 - [c74]Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang:
Novel wire density driven full-chip routing for CMP variation control. ICCAD 2007: 831-838 - [c73]Shao-Yi Chien, Chi-Sheng Shih, Mong-Kai Ku, Chia-Lin Yang, Yao-Wen Chang, Tei-Wei Kuo, Liang-Gee Chen:
3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design. ICME 2007: 9 - [c72]Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
Post-placement leakage optimization for partially dynamically reconfigurable FPGAs. ISLPED 2007: 92-97 - [c71]Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang:
X-architecture placement based on effective wire models. ISPD 2007: 87-94 - [c70]Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang:
Efficient obstacle-avoiding rectilinear steiner tree construction. ISPD 2007: 127-134 - [c69]Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jiang, Yao-Wen Chang:
A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits. PATMOS 2007: 148-159 - [c68]I-Jye Lin, Tsui-Yee Ling, Yao-Wen Chang:
Statistical circuit optimization considering device andinterconnect process variations. SLIP 2007: 47-54 - [c67]Chen-Feng Chang, Yao-Wen Chang:
X-Route: An X-architecture full-chip multilevel router. SoCC 2007: 229-232 - [p1]Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang:
NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs. Modern Circuit Placement 2007: 289-309 - 2006
- [j27]Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen:
Multilevel routing with jumper insertion for antenna avoidance. Integr. 39(4): 420-432 (2006) - [j26]Tung-Chieh Chen, Yao-Wen Chang:
Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4): 637-650 (2006) - [j25]Shang-Wei Tu, Yao-Wen Chang, Jing-Yang Jou:
RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2258-2264 (2006) - [j24]Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen:
IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2513-2525 (2006) - [j23]Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou:
Reliable crosstalk-driven interconnect optimization. ACM Trans. Design Autom. Electr. Syst. 11(1): 88-103 (2006) - [c66]Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, Jyh-Herng Wang:
Simultaneous block and I/O buffer floorplanning for flip-chip design. ASP-DAC 2006: 213-218 - [c65]Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen:
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. ASP-DAC 2006: 366-371 - [c64]Tai-Chen Chen, Yao-Wen Chang, Shyh-Chang Lin:
A novel framework for multilevel full-chip gridless routing. ASP-DAC 2006: 636-641 - [c63]Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han:
Novel full-chip gridless routing considering double-via insertion. DAC 2006: 755-760 - [c62]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
Placement of digital microfluidic biochips using the t-tree formulation. DAC 2006: 931-934 - [c61]Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang:
A high-quality mixed-size analytical placer considering preplaced blocks and density constraints. ICCAD 2006: 187-192 - [c60]Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang:
Voltage island aware floorplanning for power and timing optimization. ICCAD 2006: 389-394 - [c59]Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Wei-Ting Tu, Chih-Hung Liu, Yao-Wen Chang, Sy-Yen Kuo:
Current path analysis for electrostatic discharge protection. ICCAD 2006: 510-515 - [c58]Zhe-Wei Jiang, Yao-Wen Chang:
An optimal simultaneous diode/jumper insertion algorithm for antenna fixing. ICCAD 2006: 669-674 - [c57]Chun-Ying Lai, Shyh-Kang Jeng, Yao-Wen Chang, Chia-Chun Tsai:
Inductance extraction for general interconnect structures. ISCAS 2006 - [c56]Bor-Yiing Su, Yao-Wen Chang, Jiang Hu:
An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles. ISPD 2006: 56-63 - [c55]Chen-Wei Liu, Yao-Wen Chang:
Floorplan and power/ground network co-synthesis for fast design convergence. ISPD 2006: 86-93 - [c54]Zhe-Wei Jiang, Tung-Chieh Chen, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang:
NTUplace2: a hybrid placer using partitioning and analytical techniques. ISPD 2006: 215-217 - 2005
- [j22]Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Lee:
Crosstalk- and performance-driven multilevel full-chip routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(6): 869-878 (2005) - [j21]Jai-Ming Lin, Yao-Wen Chang:
TCG: A transitive closure graph-based representation for general floorplans. IEEE Trans. Very Large Scale Integr. Syst. 13(2): 288-292 (2005) - [c53]Jai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hui Chuang:
Placement with symmetry constraints for analog layout design using TCG-S. ASP-DAC 2005: 1135-1137 - [c52]Tai-Chen Chen, Yao-Wen Chang:
Multilevel full-chip gridless routing considering optical proximity correction. ASP-DAC 2005: 1160-1163 - [c51]Jen-Yi Wuu, Tung-Chieh Chen, Yao-Wen Chang:
SoC test scheduling using the B-tree based floorplanning technique. ASP-DAC 2005: 1188-1191 - [c50]Bor-Yiing Su, Yao-Wen Chang:
An exact jumper insertion algorithm for antenna effect avoidance/fixing. DAC 2005: 325-328 - [c49]Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, Sao-Jie Chen:
Multilevel full-chip routing for the X-based architecture. DAC 2005: 597-602 - [c48]Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin:
IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs. ICCAD 2005: 159-164 - [c47]Jia-Wei Fang, I-Jye Lin, Ping-Hung Yuh, Yao-Wen Chang, Jyh-Herng Wang:
A routing algorithm for flip-chip design. ICCAD 2005: 753-758 - [c46]Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang:
RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction. ISCAS (4) 2005: 4134-4137 - [c45]Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang:
Joint exploration of architectural and physical design spaces with thermal consideration. ISLPED 2005: 123-126 - [c44]Tung-Chieh Chen, Yao-Wen Chang:
Modern floorplanning based on fast simulated annealing. ISPD 2005: 104-112 - [c43]Tung-Chieh Chen, Tien-Chang Hsu, Zhe-Wei Jiang, Yao-Wen Chang:
NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs. ISPD 2005: 236-238 - [c42]Chi-Sheng Shih, Chia-Lin Yang, Mong-Kai Ku, Tei-Wei Kuo, Shao-Yi Chien, Yao-Wen Chang, Liang-Gee Chen:
Reconfigurable Platform for Content Science Research. RTCSA 2005: 481-486 - [c41]Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen:
Multilevel full-chip routing with testability and yield enhancement. SLIP 2005: 29-36 - 2004
- [j20]Guang-Ming Wu, Mango Chia-Tso Chao, Yao-Wen Chang:
A clustering- and probability-based approach for time-multiplexed FPGA partitioning. Integr. 38(2): 245-265 (2004) - [j19]Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao:
Simultaneous floor plan and buffer-block optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5): 694-703 (2004) - [j18]Yao-Wen Chang, Shih-Ping Lin:
MR: a new framework for multilevel full-chip routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5): 793-800 (2004) - [j17]Jai-Ming Lin, Yao-Wen Chang:
TCG-S: orthogonal coupling of P*-admissible representations for general floorplans. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(6): 968-980 (2004) - [j16]Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang:
Timing modeling and optimization under the transmission line model. IEEE Trans. Very Large Scale Integr. Syst. 12(1): 28-41 (2004) - [c40]Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang:
Layout techniques for on-chip interconnect inductance reduction. ASP-DAC 2004: 269-273 - [c39]Yi-Hui Cheng, Yao-Wen Chang:
Integrating buffer planning with floorplanning for simultaneous multi-objective optimization. ASP-DAC 2004: 624-627 - [c38]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen:
Temporal floorplanning using 3D-subTCG. ASP-DAC 2004: 725-730 - [c37]Su-Wei Wu, Yao-Wen Chang:
Efficient power/ground network analysis for power integrity-driven design methodology. DAC 2004: 177-180 - [c36]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
Temporal floorplanning using the T-tree formulation. ICCAD 2004: 300-305 - [c35]Meng-Chen Wu, Yao-Wen Chang:
Placement with Alignment and Performance Constraints Using the B*-Tree Representation. ICCD 2004: 568-571 - [c34]Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang:
RLC effects on worst-case switching pattern for on-chip buses. ISCAS (2) 2004: 945-948 - [c33]Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen:
Multilevel routing with antenna avoidance. ISPD 2004: 34-40 - [c32]Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen:
Multilevel routing with jumper insertion for antenna avoidance. SoCC 2004: 63-66 - 2003
- [j15]Yao-Wen Chang, Kai Zhu, Guang-Ming Wu, D. F. Wong, C. K. Wong:
Analysis of FPGA/FPIC switch modules. ACM Trans. Design Autom. Electr. Syst. 8(1): 11-37 (2003) - [j14]Guang-Ming Wu, Yun-Chih Chang, Yao-Wen Chang:
Rectilinear block placement using B*-trees. ACM Trans. Design Autom. Electr. Syst. 8(2): 188-202 (2003) - [j13]Jai-Ming Lin, Yao-Wen Chang, Shih-Ping Lin:
Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 679-686 (2003) - [c31]Katherine Shu-Min Li, Yih-Huai Cherng, Yao-Wen Chang:
Noise-aware buffer planning for interconnect-driven floorplanning. ASP-DAC 2003: 423-426 - [c30]Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao:
Simultaneous floorplanning and buffer block planning. ASP-DAC 2003: 431-434 - [c29]Jai-Ming Lin, Song-Ra Pan, Yao-Wen Chang:
Graph matching-based algorithms for array-based FPGA segmentation design and routing. ASP-DAC 2003: 851-854 - [c28]Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hannah Honghua Yang:
Multilevel floorplanning/placement for large-scale modules using B*-trees. DAC 2003: 812-817 - [c27]Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Lee:
A Fast Crosstalk- and Performance-Driven Multilevel Routing System. ICCAD 2003: 382-387 - 2002
- [j12]Hongbing Fan, Yu-Liang Wu, Yao-Wen Chang:
Comment on Generic Universal Switch Blocks. IEEE Trans. Computers 51(1): 93-96 (2002) - [j11]Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang:
Performance-driven placement for dynamically reconfigurable FPGAs. ACM Trans. Design Autom. Electr. Syst. 7(4): 628-642 (2002) - [j10]Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang:
Arbitrarily shaped rectilinear module placement using the transitive closure graph representation. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 886-901 (2002) - [j9]Yu-Min Lee, Charlie Chung-Ping Chen, Yao-Wen Chang, Martin D. F. Wong:
Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation. VLSI Design 15(3): 587-594 (2002) - [c26]Jai-Ming Lin, Yao-Wen Chang:
TCG-S: orthogonal coupling of P*-admissible representations for general floorplans. DAC 2002: 842-847 - [c25]Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang:
Arbitrary Convex and Concave Rectilinear Module Packing Using TCG. DATE 2002: 69-75 - [c24]Shih-Ping Lin, Yao-Wen Chang:
A novel framework for multilevel routing considering routability and performance. ICCAD 2002: 44-50 - [c23]Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-Ru Jiang:
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. ISQED 2002: 523-528 - 2001
- [j8]Yao-Wen Chang, Jai-Ming Lin, Martin D. F. Wong:
Matching-based algorithm for FPGA channel segmentation design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(6): 784-791 (2001) - [j7]Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang:
Generic ILP-based approaches for time-multiplexed FPGA partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(10): 1266-1274 (2001) - [c22]Jai-Ming Lin, Yao-Wen Chang:
TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans. DAC 2001: 764-769 - [c21]Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang:
Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model. ICCD 2001: 192-198 - [c20]Guang-Ming Wu, Jai-Ming Lin, Mango Chia-Tso Chao, Yao-Wen Chang:
Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning. ICCD 2001: 335-347 - [c19]Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang:
An Algorithm for Dynamically Reconfigurable FPGA Placement. ICCD 2001: 501-504 - 2000
- [j6]Michael Shyu, Guang-Ming Wu, Yu-Dong Chang, Yao-Wen Chang:
Generic Universal Switch Blocks. IEEE Trans. Computers 49(4): 348-359 (2000) - [j5]Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou:
Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9): 999-1010 (2000) - [j4]Yao-Wen Chang, Kai Zhu, D. F. Wong:
Timing-driven routing for symmetrical array-based FPGAs. ACM Trans. Design Autom. Electr. Syst. 5(3): 433-450 (2000) - [c18]Yun-Chih Chang, Yao-Wen Chang, Guang-Ming Wu, Shu-Wei Wu:
B*-Trees: a new representation for non-slicing floorplans. DAC 2000: 458-463 - [c17]Yao-Wen Chang, Yu-Tsang Chang:
An architecture-driven metric for simultaneous placement and global routing for FPGAs. DAC 2000: 567-572 - [c16]Guang-Ming Wu, Yun-Chih Chang, Yao-Wen Chang:
Rectilinear Block Placement Using B*-Trees. ICCD 2000: 351-356 - [c15]Song-Ra Pan, Yao-Wen Chang:
Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation. ICCD 2000: 581-584 - [c14]Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou:
Optimal reliable crosstalk-driven interconnect optimization. ISPD 2000: 128-133
1990 – 1999
- 1999
- [j3]Guang-Ming Wu, Yao-Wen Chang:
Quasi-Universal Switch Matrices for FPD Design. IEEE Trans. Computers 48(10): 1107-1122 (1999) - [c13]Iris Hui-Ru Jiang, Jing-Yang Jou, Yao-Wen Chang:
Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. DAC 1999: 90-95 - [c12]Guang-Ming Wu, Michael Shyu, Yao-Wen Chang:
Universal Switch Blocks for Three-Dimensional FPGA Design. FPGA 1999: 254 - [c11]Mango Chia-Tso Chao, Guang-Ming Wu, Iris Hui-Ru Jiang, Yao-Wen Chang:
A clustering- and probability-based approach for time-multiplexed FPGA partitioning. ICCAD 1999: 364-369 - [c10]Michael Shyu, Yu-Dong Chang, Guang-Ming Wu, Yao-Wen Chang:
Generic Universal Switch Blocks. ICCD 1999: 311-314 - 1998
- [c9]Yao-Wen Chang, Jai-Ming Lin, D. F. Wong:
Graph matching-based algorithms for FPGA segmentation design. ICCAD 1998: 34-39 - [c8]Kai Zhu, Yao-Wen Chang, D. F. Wong:
Timing-driven routing for symmetrical-array-based FPGAs. ICCD 1998: 628-633 - [c7]Guang-Ming Wu, Yao-Wen Chang:
Switch-matrix architecture and routing for FPDs. ISPD 1998: 158-163 - 1997
- [j2]Shashidhar Thakur, Yao-Wen Chang, Martin D. F. Wong, S. Muthukrishnan:
Algorithms for an FPGA switch module routing problem with application to global routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(1): 32-46 (1997) - 1996
- [j1]Yao-Wen Chang, D. F. Wong, C. K. Wong:
Universal switch modules for FPGA design. ACM Trans. Design Autom. Electr. Syst. 1(1): 80-101 (1996) - [c6]Chung-Ping Chen, Yao-Wen Chang, D. F. Wong:
Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. DAC 1996: 405-408 - [c5]Yao-Wen Chang, D. F. Wong, C. K. Wong:
Universal Switch-Module Design for Symmetric-Array-Based FPGAs. FPGA 1996: 80-86 - 1995
- [c4]Yao-Wen Chang, D. F. Wong, C. K. Wong:
FPGA global routing based on a new congestion metric. ICCD 1995: 372-378 - [c3]Yao-Wen Chang, D. F. Wong, C. K. Wong:
Design and analysis of FPGA/FPIC switch modules. ICCD 1995: 394-401 - 1994
- [c2]Yao-Wen Chang, Shashidhar Thakur, Kai Zhu, D. F. Wong:
A new global routing algorithm for FPGAs. ICCAD 1994: 356-361 - 1993
- [c1]Kai Zhu, D. F. Wong, Yao-Wen Chang:
Switch module design with application to two-dimensional segmentation design. ICCAD 1993: 480-485
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-07 21:25 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
