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Subhasis Banerjee
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2020 – today
- 2022
- [c14]Subhasis Banerjee, Aniruddha Panda, Saurabh Chawdhary, Pandu Devarakota:
Performance Engineering for Deep Learning Adaptation of Seismic Processing Workflow. COMAD/CODS 2022: 342-343
2010 – 2019
- 2017
- [c13]Rakhi Hemani, Subhasis Banerjee, Apala Guha:
The interaction of last-level-cache mechanisms on modern processors. MEMSYS 2017: 249-250 - 2016
- [c12]Rakhi Hemani, Subhasis Banerjee, Apala Guha:
On the applicability of simple cache models for modern processors. ICGHPC 2016: 1-7 - [c11]Rakhi Hemani, Subhasis Banerjee, Apala Guha:
Easy and expressive LLC contention model. HPCS 2016: 372-379 - 2014
- [c10]Nishtha Tripathi, Subhasis Banerjee:
SARROD: SPARQL Analyzer and Reordering for Runtime Optimization on Big Data. BDA 2014: 189-196 - [c9]Subhasis Banerjee, Kalapriya Kannan:
Tag-In-Tag: Efficient flow table management in SDN switches. CNSM 2014: 109-117 - [c8]Kalapriya Kannan, Subhasis Banerjee:
FlowMaster: Early Eviction of Dead Flow on SDN Switches. ICDCN 2014: 484-498 - 2013
- [c7]Kalapriya Kannan, Subhasis Banerjee:
Compact TCAM: Flow Entry Compaction in TCAM for Power Aware SDN. ICDCN 2013: 439-444 - 2012
- [c6]Kalapriya Kannan, Subhasis Banerjee:
Scissors: Dealing with header redundancies in data centers through SDN. CNSM 2012: 295-301
2000 – 2009
- 2008
- [j3]Subhasis Banerjee, G. Surendra, S. K. Nandy:
On the effectiveness of phase based regression models to trade power and performance using dynamic processor adaptation. J. Syst. Archit. 54(8): 797-815 (2008) - 2007
- [c5]Subhasis Banerjee, G. Surendra, S. K. Nandy:
Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency. ASP-DAC 2007: 884-889 - 2006
- [j2]G. Surendra, Subhasis Banerjee, S. K. Nandy:
Instruction Reuse in SPEC, media and packet processing benchmarks: A comparative study of power, performance and related microarchitectural optimizations. J. Embed. Comput. 2(1): 15-34 (2006) - 2004
- [c4]G. Surendra, Subhasis Banerjee, S. K. Nandy:
Power-performance trade-off using pipeline delays. ASP-DAC 2004: 384-386 - [c3]Subhasis Banerjee, G. Surendra, S. K. Nandy:
Exploiting program execution phases to trade power and performance for media workload. ASP-DAC 2004: 387-389 - [c2]G. Surendra, Subhasis Banerjee, S. K. Nandy:
On the effectiveness of prefetching and reuse in reducing L1 data cache traffic: a case study of Snort. WMPI 2004: 88-95 - 2003
- [j1]G. Surendra, Subhasis Banerjee, S. K. Nandy:
On the Effectiveness of Flow Aggregation in Improving Instruction Reuse in Network Processing Applications. Int. J. Parallel Program. 31(6): 469-487 (2003) - [c1]G. Surendra, Subhasis Banerjee, S. K. Nandy:
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation. DATE 2003: 10784-10789 - [p1]G. Surendra, Subhasis Banerjee, S. K. Nandy:
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation. Embedded Software for SoC 2003: 359-371
Coauthor Index
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