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Wendelin Serwe
Person information
- affiliation: INRIA, France
- award (2023): ETAPS Test-of-Time Tool Award
- award (2021): Inria - Académie des Sciences - Dassault Systèmes Innovation Prize
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2020 – today
- 2024
- [c35]Philippe Ledent, Radu Mateescu, Wendelin Serwe:
Testing Resource Isolation for System-on-Chip Architectures. MARS@ETAPS 2024: 129-168 - 2023
- [j7]Jean-Baptiste Horel, Philippe Ledent, Lina Marsso, Lucie Muller, Christian Laugier, Radu Mateescu, Anshul Paigwar, Alessandro Renzaglia, Wendelin Serwe:
Verifying Collision Risk Estimation using Autonomous Driving Scenarios Derived from a Formal Model. J. Intell. Robotic Syst. 107(4): 59 (2023) - 2022
- [c34]Jean-Baptiste Horel, Christian Laugier, Lina Marsso, Radu Mateescu, Lucie Muller, Anshul Paigwar, Alessandro Renzaglia
, Wendelin Serwe:
Using Formal Conformance Testing to Generate Scenarios for Autonomous Vehicles. DATE 2022: 532-537 - [c33]Lina Marsso, Radu Mateescu, Lucie Muller, Wendelin Serwe:
Formally Modeling Autonomous Vehicles in LNT for Simulation and Testing. MARS@ETAPS 2022: 60-117 - 2021
- [c32]Hubert Garavel, Frédéric Lang, Radu Mateescu, Wendelin Serwe:
Is CADP an Applicable Formal Method? AppFM@FM 2021: 1-11 - 2020
- [c31]Luca Di Stefano
, Frédéric Lang, Wendelin Serwe:
Combining SLiVER with CADP to Analyze Multi-agent Systems. COORDINATION 2020: 370-385 - [c30]Lina Marsso, Radu Mateescu, Wendelin Serwe:
Automated Transition Coverage in Behavioural Conformance Testing. ICTSS 2020: 219-235 - [c29]Radu Mateescu, Wendelin Serwe, Aymane Bouzafour, Marc Renaudin:
Modeling an Asynchronous Circuit Dedicated to the Protection Against Physical Attacks. MARS@ETAPS 2020: 200-239
2010 – 2019
- 2019
- [c28]Viet-Anh Nguyen, Wendelin Serwe, Radu Mateescu, Eric Jenn:
Hunting Superfluous Locks with Model Checking. From Software Engineering to Formal Methods and Tools, and Back 2019: 416-432 - [c27]Lina Marsso, Radu Mateescu, Ioannis Parissis, Wendelin Serwe:
Asynchronous Testing of Synchronous Components in GALS Systems. IFM 2019: 360-378 - 2018
- [c26]Aymane Bouzafour, Marc Renaudin, Hubert Garavel, Radu Mateescu, Wendelin Serwe:
Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits. ASYNC 2018: 34-42 - [c25]Birgit Hofer, Radu Mateescu, Wendelin Serwe, Franz Wotawa:
Using LNT Formal Descriptions for Model-Based Diagnosis. DX 2018 - [c24]Lina Marsso, Radu Mateescu, Wendelin Serwe:
TESTOR: A Modular Tool for On-the-Fly Conformance Test Case Generation. TACAS (2) 2018: 211-228 - [e1]John P. Gallagher, Rob van Glabbeek, Wendelin Serwe:
Proceedings Third Workshop on Models for Formal Analysis of Real Systems and Sixth International Workshop on Verification and Program Transformation, MARS/VPT@ETAPS 2018, Thessaloniki, Greece, 20th April 2018. EPTCS 268, 2018 [contents] - 2017
- [c23]Hubert Garavel, Frédéric Lang, Wendelin Serwe:
From LOTOS to LNT. ModelEd, TestEd, TrustEd 2017: 3-26 - [c22]Hubert Garavel, Wendelin Serwe:
The Unheralded Value of the Multiway Rendezvous: Illustration with the Production Cell Benchmark. MARS@ETAPS 2017: 230-270 - 2016
- [j6]Zhen Zhang, Wendelin Serwe, Jian Wu, Tomohiro Yoneda, Hao Zheng, Chris J. Myers
:
An improved fault-tolerant routing algorithm for a Network-on-Chip derived with formal analysis. Sci. Comput. Program. 118: 24-39 (2016) - 2015
- [c21]Abderahman Kriouile, Wendelin Serwe:
Using a Formal Model to Improve Verification of a Cache-Coherent System-on-Chip. TACAS 2015: 708-722 - [c20]Wendelin Serwe:
Formal Specification and Verification of Fully Asynchronous Implementations of the Data Encryption Standard. MARS 2015: 61-147 - 2014
- [j5]Etienne Lantreibecq, Wendelin Serwe:
Formal analysis of a hardware dynamic task dispatcher with CADP. Sci. Comput. Program. 80: 130-149 (2014) - [c19]Zhen Zhang, Wendelin Serwe, Jian Wu, Tomohiro Yoneda, Hao Zheng, Chris J. Myers
:
Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip. FMICS 2014: 48-62 - 2013
- [j4]Radu Mateescu, Wendelin Serwe:
Model checking and performance evaluation with CADP illustrated on shared-memory mutual exclusion protocols. Sci. Comput. Program. 78(7): 843-861 (2013) - [j3]Hubert Garavel, Frédéric Lang, Radu Mateescu, Wendelin Serwe:
CADP 2011: a toolbox for the construction and analysis of distributed processes. Int. J. Softw. Tools Technol. Transf. 15(2): 89-107 (2013) - [c18]Abderahman Kriouile, Wendelin Serwe:
Formal Analysis of the ACE Specification for Cache Coherent Systems-on-Chip. FMICS 2013: 108-122 - 2012
- [c17]Hubert Garavel, Radu Mateescu, Wendelin Serwe:
Large-scale Distributed Verification Using CADP: Beyond Clusters to Grids. PASM/PDMC 2012: 145-161 - 2011
- [c16]Etienne Lantreibecq, Wendelin Serwe:
Model Checking and Co-simulation of a Dynamic Task Dispatcher Circuit Using CADP. FMICS 2011: 180-195 - [c15]Hubert Garavel, Frédéric Lang, Radu Mateescu, Wendelin Serwe:
CADP 2010: A Toolbox for the Construction and Analysis of Distributed Processes. TACAS 2011: 372-387 - 2010
- [c14]Radu Mateescu, Wendelin Serwe:
A Study of Shared-Memory Mutual Exclusion Protocols Using CADP. FMICS 2010: 180-197 - [c13]Nicolas Coste, Hubert Garavel, Holger Hermanns, Frédéric Lang, Radu Mateescu, Wendelin Serwe:
Ten Years of Performance Evaluation for Concurrent Systems Using CADP. ISoLA (2) 2010: 128-142
2000 – 2009
- 2009
- [j2]Hubert Garavel, Gwen Salaün, Wendelin Serwe:
On the semantics of communicating hardware processes and their translation into LOTOS for the verification of asynchronous circuits with CADP. Sci. Comput. Program. 74(3): 100-127 (2009) - [c12]Nicolas Coste, Holger Hermanns, Etienne Lantreibecq, Wendelin Serwe:
Towards Performance Prediction of Compositional Models in Industrial GALS Designs. CAV 2009: 204-218 - [c11]Hubert Garavel, Claude Helmstetter
, Olivier Ponsini, Wendelin Serwe:
Verification of an industrial SystemC/TLM model using LOTOS and CADP. MEMOCODE 2009: 46-55 - 2008
- [c10]Olivier Ponsini, Wendelin Serwe:
A Schedulerless Semantics of TLM Models Written in SystemC Via Translation into LOTOS. FM 2008: 278-293 - 2007
- [c9]Gwen Salaün, Wendelin Serwe, Yvain Thonnart, Pascal Vivet:
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip. ASYNC 2007: 73-82 - [c8]Hubert Garavel, Radu Mateescu, Frédéric Lang, Wendelin Serwe:
CADP 2006: A Toolbox for the Construction and Analysis of Distributed Processes. CAV 2007: 158-163 - 2006
- [j1]Hubert Garavel, Wendelin Serwe:
State space reduction for process algebra specifications. Theor. Comput. Sci. 351(2): 131-145 (2006) - 2005
- [c7]Gwen Salaün, Wendelin Serwe:
Translating Hardware Process Algebras into Standard Process Algebras: Illustration with CHP and LOTOS. IFM 2005: 287-306 - 2004
- [c6]Hubert Garavel, Wendelin Serwe:
State Space Reduction for Process Algebra Specifications. AMAST 2004: 164-180 - [c5]Bertrand Jeannet, Wendelin Serwe:
Abstracting Call-Stacks for Interprocedural Verification of Imperative Programs. AMAST 2004: 258-273 - 2003
- [c4]Rachid Echahed, Frédéric Prost, Wendelin Serwe:
Statically assuring secrecy for dynamic concurrent processes. PPDP 2003: 91-101 - 2002
- [b1]Wendelin Serwe:
Etude de la programmation logico-fonctionnelle concurrente. Grenoble Institute of Technology, France, 2002 - 2001
- [c3]Jérémie Blanc, Wendelin Serwe:
Timed Term Rewrite Systems. WFLP 2001: 95-112 - [c2]Rachid Echahed, Wendelin Serwe:
Defining Actions in Concurrent Declarative Programming. WFLP 2001: 176-194 - 2000
- [c1]Rachid Echahed, Wendelin Serwe:
Combining Mobile Processes and Declarative Programming. Computational Logic 2000: 300-314
Coauthor Index
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last updated on 2024-06-13 20:57 CEST by the dblp team
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