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ORCID24th ASYNC 2018: Vienna, Austria
- 24th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2018, Vienna, Austria, May 13-16, 2018. IEEE Computer Society 2018, ISBN 978-1-5386-5883-3
Paper Session 1: Building Blocks of Asynchronous Circuits
- Masashi Imai, Shinichiro Akasaka, Tomohiro Yoneda:
Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase Handshaking Protocols. 1-8 - Alberto Moreno
, Jordi Cortadella:
State Encoding of Asynchronous Controllers Using Pseudo-Boolean Optimization. 9-16 - Florian Huemer, Andreas Steininger:
Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication. 17-25
Industrial Session 1: Design Flow
- Yang Zhang, Huimei Cheng, Dake Chen, Huayu Fu, Shikhanshu Agarwal, Mark Lin, Peter A. Beerel:
Challenges in Building an Open-Source Flow from RTL to Bundled-Data Design. 26-27 - Sophie Germain, Sylvain Engels, Laurent Fesquet:
A Design Flow for Shaping Electromagnetic Emissions in Micropipeline Circuits. 28-29 - Danil Sokolov, Victor Khomenko, Alex Yakovlev, David Lloyd:
Design and Verification of Speed-Independent Circuits with Arbitration in Workcraft. 30-31
Industrial & Fresh Idea Paper Session 2: New Applications
- Andrew Lines, Prasad Joshi, Ruokun Liu, Steve McCoy, Jonathan Tse, Yi-Hsin Weng, Mike Davies:
Loihi Asynchronous Neuromorphic Research Chip. 32-33
Paper Session 3: Formal Methods for Design and Verification
- Aymane Bouzafour, Marc Renaudin, Hubert Garavel, Radu Mateescu, Wendelin Serwe:
Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits. 34-42 - Ghaith Tarawneh, Andrey Mokhov:
Formal Verification of Mixed Synchronous Asynchronous Systems Using Industrial Tools. 43-50 - Cuong K. Chau, Warren A. Hunt Jr., Matt Kaufmann, Marly Roncken, Ivan E. Sutherland:
Data-Loop-Free Self-Timed Circuit Verification. 51-58
Paper Session 4: Metastability and Synchronization
- Justin Reiher, Mark R. Greenstreet, Ian W. Jones:
Explaining Metastability in Real Synchronizers. 59-67 - Matthias Függer, Attila Kinali, Christoph Lenzen, Ben Wiederhake:
Fast All-Digital Clock Frequency Adaptation Circuit for Voltage Droop Tolerance. 68-77
Paper Session 5: New Application Horizons
- Sam Fok, Kwabena Boahen:
A Serial H-Tree Router for Two-Dimensional Arrays. 78-85 - Christoph Hoppe, Jens Döge, Peter Reichel, Patrick Russell, Andreas Reichel, Peter Schneider:
A High Speed Asynchronous Multi Input Pipeline for Compaction and Transfer of Parallel SIMD Data. 86-92 - Ning Qiao, Giacomo Indiveri:
A Clock-Less Ultra-Low Power Bit-Serial LVDS Link for Address-Event Multi-chip Systems. 93-101
Paper Session 7: Chip Design, Analysis and Verification
- Oyinkuro Benafa, Danil Sokolov, Alex Yakovlev:
Loadable Kessels Counter. 102-109 - Gregoire Gimenez, Abdelkarim Cherkaoui, Guillaume Cogniard, Laurent Fesquet:
Static Timing Analysis of Asynchronous Bundled-Data Circuits. 110-118
Industrial & Fresh Idea Paper Session 8: Open Questions
- Shomit Das, Michael LeBeane, Bradford M. Beckmann, Greg Sadowski:
Case Study of Process Variation-Based Domain Partitioning of GPGPUs. 119-120
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