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ORCIDHarry J. M. Veendrick
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2000 – 2009
- 2006
[c7]Violeta Petrescu, Marcel J. M. Pelgrom, Harry J. M. Veendrick, Praveen Pavithran, Jean Wieling:
A Signal-Integrity Self-Test Concept for Debugging Nanometer CMOS ICs. ISSCC 2006: 2220-2229- 2005
- [c6]Atul Katoch, Harry J. M. Veendrick:
Isodelay output driver design using step-wise charging for low power. ESSCIRC 2005: 149-152 - [c5]Atul Katoch, Harry J. M. Veendrick, Evert Seevinck:
High speed current-mode signaling circuits for on-chip interconnects. ISCAS (4) 2005: 4138-4141 - 2004
- [c4]Atul Katoch, Manish Garg, Evert Seevinck, Harry J. M. Veendrick:
Adaptive threshold scheme to operate long on-chip buses at the limit of signal integrity. ESSCIRC 2004: 323-326 - 2003
- [c3]Rohini Krishnan, José Pineda de Gyvez, Harry J. M. Veendrick:
Encoded-Low Swing Technique for Ultra Low Power Interconnect. FPL 2003: 240-251
1990 – 1999
- 1999
- [c2]Ivo Bolsens, Wojtek Maly, Ludo Deferm, Jo Borel, Harry J. M. Veendrick:
Single Chip or Hybrid System Integration. DATE 1999: 616- - 1995
- [j1]Kees A. Vissers, Gerben Essink, Piet J. van Gerwen, P. J. M. Janssen, O. Popp, E. Riddersma, W. J. M. Smits, Harry J. M. Veendrick:
Architecture and programming of two generations video signal processors. Microprocess. Microprogramming 41(5-6): 373-390 (1995) - 1990
- [c1]Dick W. Harberts, Dré A. J. M. van den Elshout, Harry J. M. Veendrick:
Design for routability of a high-density gate array. ICCD 1990: 56-59
Coauthor Index
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