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1990 – 1999
- 1996
[c7]Jos van Sas, Urbain Swerts, Marc Darquennes:
Towards an Effective IDDQ Test Vector Selection and Application Methodology. ITC 1996: 491-500- 1995
- [c6]Jos van Sas, Erik Huyskens, Hans Naert, Fred Schell, Ad J. van de Goor:
Coping with Re-usability Using Sequential ATPG: A Practical Case Study. ITC 1995: 252-261 - 1994
- [j5]Jos van Sas, Chay Nowé, Didier Pollet, Francky Catthoor, Paul Vanoostende, Hugo De Man:
Design of a C-testable booth multiplier using a realistic fault model. J. Electron. Test. 5(1): 29-41 (1994) - [j4]Jos van Sas, Francky Catthoor, Hugo De Man:
Cellular automata based deterministic self-test strategies for programmable data paths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(7): 940-949 (1994) - [c5]Hans A. R. Manhaeve, Paul L. Wrighton, Jos van Sas, Urbain Swerts:
An Off-chip IDDQ Current Measurement Unit for Telecommunication ASICs. ITC 1994: 203-212 - 1993
- [j3]Jos van Sas, Francky Catthoor, Hugo De Man:
Test Algorithms for Double-Buffered Random Access and Pointer-Addressed Memories. IEEE Des. Test Comput. 10(2): 34-44 (1993) - [c4]Jos van Sas, Geert van Wauwe, Erik Huyskens, Dirk Rabaey:
BIST for Embedded Static RAMs with Coverage Calculation. ITC 1993: 339-348 - 1992
- [c3]Jos van Sas, Francky Catthoor, Hugo De Man:
Optimized BIST Strategies for Programmable Data Paths Based on Cellular Automata. ITC 1992: 110-119 - 1991
- [c2]Jos van Sas, Francky Catthoor, Peter Vandeput, Frank Rossaert, Hugo De Man:
Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment. EURO-DAC 1991: 208-213 - 1990
- [j2]Jos van Sas, Francky Catthoor, Luc Inzé, Hugo De Man:
Testability strategy and test pattern generation for register files and customized memories. Microprocess. Microsystems 14(7): 444-456 (1990) - [c1]Jos van Sas, Francky Catthoor, Hugo De Man:
Cellular automata based self-test for programmable data paths. ITC 1990: 769-778
1980 – 1989
- 1989
- [j1]Francky Catthoor, Jos van Sas, Luc Inzé, Hugo De Man:
A testability strategy for multiprocessor architecture. IEEE Des. Test 6(2): 18-34 (1989)
Coauthor Index
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