default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDITC 1993: Baltimore, MD, USA
- Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics - Join Them, Baltimore, Maryland, USA, October 17-21, 1993. IEEE Computer Society 1993, ISBN 0-7803-1430-1
Plenary
- Joseph B. Costello:
Design and Test: What Will It Take to Tie the Knot? ITC 1993: 18 - Michael S. Ledford:
Automotive Industry: The Next DFT Challenge. ITC 1993: 19
System Testing
- Colin M. Maunder:
A Universal Framework for Managed Built-in Test. 21-29 - William R. Simpson, John W. Sheppard:
The Impact of Commercial Off-The-Shelf (COTS) Equipment on System Test and Diagnosis. 30-36 - Israel Beniaminy, Moshe Ben-Bassat, M. Bodenheimer, M. Eshel:
Experience in Diagnosing a Remote, Tele-Controlled Unit Using the AITEST Expert System. 37-44 - Frank W. Angelotti, Wayne A. Britson, Kerry T. Kaliszewski, Steve M. Douskey:
System Level Interconnect Test in a Tristate Environment. 45-53
I-DDQ And Logic Testing of CMOS Bridging
- Jeff Rearick, Janak H. Patel:
Fast and Accurate CMOS Bridging Fault Simulation. 54-62 - Peter C. Maxwell, Robert C. Aitken:
Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic. 63-72 - Eugeni Isern
, Joan Figueras:
Test Generation with High Coverages for Quiescent Current Test of Bridging Faults in Combinational Circuits. 73-82 - Heinrich Theodor Vierhaus, Wolfgang Meyer, Uwe Gläser:
CMOS Bridges and Resistive Transistor Faults: IDDQ versus Delay Effects. 83-91
SPC-Based Intelligent Test
- Kurt A. Milne:
Automated Wafer Lot Approval: A Statistically Based Implementation. 92-98 - Brian Beck:
Practical Application of Statistical Process Control in Semiconductor Manufacturing. 99-107 - Rick Boyle, Jack Donovan, Eugene R. Hnatek, Alex M. Ijaz:
Application of Statistical Techniques to Critical System Parameters. 108-114 - M. M. A. van Rosmalen, Keith Baker, Eric Bruls, Jochen A. G. Jess:
Parameter Monitoring: Advantages and Pitfalls. 115-124
Advancement In Test Generation
- Tom Austin:
Creating A Mixed-Signal Simulation Capability for Concurrent IC Design and Test Program Development. 125-132 - Tony Taylor:
Tools and Techniques for Converting Simulation Models into Test Patterns. 133-138 - Ravindranath Naiknaware, G. N. Nandakumar, Srinivasa Rao Kasa:
Automatic Test Plan Generation for Analog and Mixed Signal Integrated Circuits using Partial Activation and High Level Simulation. 139-148 - Jan Moorman, Steven D. Millman:
Visualizing Test Information: A Novel Approach for Improving Testability. 149-156
IEEE STD 1149.1 In Action
- Markus Robinson, Frédéric Mailhot, Jim Konsevich:
Technology Independent Boundary Scan Synthesis (Technology and Physical Issues). 157-166 - Tom Langford:
Utilizing Boundary Scan to Implement BIST. 167-173 - Math Muris, Alex S. Biewenga:
Using Boundary Scan Test to Test Random Access Memory Clusters. 174-179
Software Testability
- Jarir K. Chaar, Michael J. Halliday, Inderpal S. Bhandari, Ram Chillarege:
On the Evaluation of Software Inspections and Tests. 180-189 - Samuel T. Chanson, Antonio Alfredo Ferreira Loureiro, Son T. Vuong:
On the Design for Testability of Communication Software. 190-199 - Gregory F. Sullivan, Dwight S. Wilson, Gerald M. Masson:
Certification Trails and Software Design for Testability. 200-209
Cost-Effective Application Of Ate
- Chryssa Dislis, J. H. Dick, I. D. Dear, I. N. Azu, Anthony P. Ambler:
Economics Modelling for the Determination of Test Strategies for Complex VLSI Boards. 210-217 - Richard H. Williams, Charles F. Hawkins:
The Economics of Guardband Placement. 218-225 - Douglas J. Mirizzi, Willie Jerrels, Dale Ohmart:
Implementation of Parallelsite Test on an 8Bit Configurable Microcontroller. 226-235
Delay Testing - Self Test
- Slawomir Pilarski, Alicja Pierzynska:
BIST and Delay Fault Detection. 236-242 - Prab Varma, Tushar Gheewala:
Delay Testing Using a Matrix of Accessible Storage. 243-252 - Harold N. Scholz, Duane R. Aadsen, Yervant Zorian:
A Method for Delay Fault Self-Testing of Macrocells. 253-261
Panel: IEEE STD 1149.1: Barriers - Real and Irrational!
- Colin M. Maunder:
Position Statement: ITC93 Boundary-Scan Panel. ITC 1993: 262 - David A. Greene:
Benefits of Boundary-Scan to In-Circuit Test. 263 - Wayne T. Daniel:
IEEE 1149.1 Growing Pains. ITC 1993: 264 - Mick Tegethoff:
IEEE 1149.1: How to Justify Implementation. ITC 1993: 265
Panel: Known Good Die: A Key To Cost Effective MCMs
- David C. Keezer:
Known Godd Die for MCMs: Enabling Technologies. 266
Panel: DFT - Profit Or Loss?
- Prab Varma:
Scan DFT: Why More Can Cost Less. 267 - John W. Sheppard:
Testing Fully Testable Systems: A Case Study. 268 - Jon Turino:
DFT: Profit or Loss -- A Position Paper. 269
Panel: Software Testing Got You Down?
- Alex Elentukh:
Cultural Evolution in Software Testing. 270 - Michael A. Long:
Software Regression Testing Success Story. 271-272 - James F. Leathrum, K. A. Liburdy:
The Evolving Role of Testing in Open Systems Standards. 273-274
How Can CMOS IC Quality Be Improved?
- Hong Hao, Edward J. McCluskey:
Very-Low-Voltage Testing for Weak CMOS Logic ICs. 275-284 - Rick Gayle:
The Cost of Quality: Reducing ASIC Defects with IDDQ At-Speed Testing and Increased Fault Coverage. 285-292 - Paul C. Wiscombe:
A Comparison of Stuck-At Fault Coverage and IDDQ Testing on Defect Levels. 293-299
Testability Structures For Mixed-Signal Board Testing
- Carl W. Thatcher, Rodham E. Tulloss:
Towards a Test Standard for Board and System Level Mixed-Signal Interconnects. 300-308 - Kenneth P. Parker, John E. McDermid, Stig Oresjo:
Structure and Metrology for an Analog Testability Bus. 309-322 - José Silva Matos, Ana C. Leão, João Canas Ferreira:
Control and Observation of Analog Nodes in Mixed-Signal Boards. 323-331
On-Product Bist
- Robert Gage:
Structured CBIST in ASICs. 332-338 - Jos van Sas, Geert van Wauwe, Erik Huyskens, Dirk Rabaey:
BIST for Embedded Static RAMs with Coverage Calculation. 339-348 - James Broseghini, Donald H. Lenhert:
An ALU-Based Programmable MISR/Pseudorandom Generator for a MC68HC11 Family Self-Test. 349-358
Multichip Module Testing
- Thomas M. Storey:
A Test Methodology for VLSI Chips on Silicon. 359-368 - Lynn Roszel:
MCM Foundry Test Methodology and Implementation. 369-372 - Russell J. Wagner, Joel A. Jorgenson:
Design-For-Test Techniques Utilized in an Avionics Computer MCM. 373-382
DFT: Putting Principles Into Practice
- Chryssa Dislis, J. H. Dick, Anthony P. Ambler:
Algorithms for Cost Optimised Test Strategy Selection. 383-391 - Cary Champlin:
IRIDIUMtm Satellite: A Large System Application of Design for Testability. 392-398 - Rodham E. Tulloss:
IEEE 1149 Standards - Changing Testing, Silicon to Systems. 399-408
Making Test Generation Faster
- Maria José Aguado, Eduardo de la Torre, Miguel Miranda, Carlos A. López-Barrio:
Distributed Implementation of an ATPG System Using Dynamic Fault Allocation. 409-418 - Robert H. Klenke, Lori M. Kaufman, James H. Aylor, Ronald Waxman, Padmini Narayan:
Workstation Based Parallel Test Generation. 419-428 - Mitsuo Teramoto:
A Method for Reducing the Search Space in Test Pattern Generation. 429-435
Test Engineering Strategies I
- Scott Diamond, Bo Janko:
Extraction of Coupled SPICE Models for Packages and Interconnects. 436-445 - Rudy Garcia:
Keep Alive - A New Requirement for High Performance uProcessor Test. 446-450 - Hans Bouwmeester, Steven Oostdijk, Frank Bouwman, Rudi Stans, Loek Thijssen, Frans P. M. Beenker:
Minimizing Test Time by Exploiting Parallelism in Macro Test. 451-460
Test Data Management
- Jim Mosley III:
A Flexible Approach to Data Collection for Component Test Systems. 461-470 - John O'Donnell:
Generated in Real-time Instant Process Statistics ("GRIPS"): Immediate, Tester-computed Test Statistics, Eliminating the Post-processing of Datalogs. 471-477 - Paresh Gondalia, Allan Gutjahr, Wen-Ben Jone:
Realizing a High Measure of Confidence for Defect Level Analysis of Random Testing. 478-487
DFT: Winning It With Partial Scan
- Johannes Steensma, Francky Catthoor, Hugo De Man:
Partial Scan at the Register-Transfer Level. 488-497 - Kee Sup Kim, Charles R. Kime:
Partial Scan Using Reverse Direction Empirical Testability. 498-506 - Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik:
PSBIST: A Partial-Scan Based Built-In Self-Test Scheme. 507-516
IEEE STD 1149.1 Design Issues
- Lee Whetsel:
Hierarchically Accessing 1149.1 Applications in a System Environment. 517-526 - Christopher Poirier:
IEEE P1149.5 to 1149.1 Data and Protocol Conversion. 527-535 - José Manuel Martins Ferreira, Manuel G. Gericota, José L. Ramalho, Gustavo R. Alves:
BIST for 1149.1-Compatible Boards: A Low-Cost and Maximum-Flexibility Solution. 536-543
Timing Systems - Analysis And Time Measurement
- Richard K. Feldman:
A Novel Instrument for Accurate Time Measurement in Automatic Calibration of Test Systems. 544-551 - Arnold Frisch, Thomas Almy:
Timing Analyzer for Embedded Testing. 552-555 - Will Creek:
Characterization of Edge Placement Accuracy in High-Speed Digital Pin Electronics. 556-565
Realistic Quality Practices
- Mani Soma:
Fault Coverage of DC Parametric Tests for Embedded Analog Amplifiers. 566-573 - E. Kurzweil, M. Lallement, R. Blanc, R. Pasquinelli:
Catch the Ground Bounce Before It Hits your System. 574-584 - Hugh Littlebury, Roger Brueckner:
Integrating Electrical Test into Final Assembly. 585-589
Panel: Mixed-Signal Test Bus: Has It Arrived?
- Carl W. Thatcher:
Design-For-Testability Economics. 590 - Nai-Chi Lee:
Practical Considerations for Mixed-Signal Test Bus. 591-592
Panel: Test Synthesis: Fact Or Fiction?
- Gunnar Carlsson:
Test Synthesis from a User Perspective. ITC 1993: 593
Panel: Fault Coverage Numbers: What Do They Really Mean?
- Miron Abramovici:
DOs and DON'Ts in Computing Fault Coverage. 594 - Peter C. Maxwell:
Let's Grade ALL the Faults. 595 - Jerry M. Soden, Charles F. Hawkins:
Quality Testing Requires Quality Thinking. 596 - Edward J. McCluskey:
Quality and Single-Stuck Faults. 597
Constrained Test Generation
- M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor:
Test Pattern Generation with Restrictors. 598-605 - Praveen Vishakantaiah, Jacob A. Abraham, Daniel G. Saab:
CHEETA: Composition of Hierarchical Sequential Tests Using ATKET. 606-615 - Eun Sei Park, M. Ray Mercer:
Switch-Level ATPG Using Constraint-Guided Line Justification. 616-625
Novel And Practical Power Supply Current Test Techniques
- J. S. Beasley, H. Ramamurthy, Jaime Ramírez-Angulo, Mark DeYong:
iDD Pulse Response Testing of Analog and Digital CMOS Circuits. 626-634 - Ching-Wen Hsue, Chih-Jen Lin:
Built-In Current Sensor for IDDQ Test in CMOS. 635-641 - Kenneth M. Wallquist, Alan W. Righter, Charles F. Hawkins:
A General Purpose IDDQ Measurement Circuit. 642-651
Board Test: Analog, Bare Board, Digital
- Naim Ben-Hamida, Bozena Kaminska:
Analog Circuit Testing Based on Sensitivity Computation and New Circuit Modeling. 652-661 - S. J. Barnfield, Will R. Moore:
Multiple Fault Diagnosis in Printed Circuit Boards. 662-671 - Christophe Vaucher, Louis Balme:
The Standard Mirror Boards (SMBs) Concept - An Innovative Improvement of Traditional ATE for up to 10 Mil Bare Board Testing. 672-679
Mixed Signal Device Test Techniques
- Anchada Charoenrook, Mani Soma:
Fault Diagnosis of Flash ADC using DNL Test. 680-689 - David Ownby, Harold Bogard:
FFT Based Troubleshooting of 120dB Dynamic Range ADC Systems. 690-696 - Shinichi Kimura, Makoto Kimura, Takayuki Nakatani, Masao Sugai:
A New Approach for PLL Characterization on Mixed Signal ATE. 697-704
Compact Delay Testing
- D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation. 705-713 - Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal:
Generation of Compact Delay Tests by Multiple-Path Activation. 714-723 - Jayashree Saxena, Dhiraj K. Pradhan:
A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits. 724-733
Synthesis And Testability
- LaNae J. Avra, Edward J. McCluskey:
Synthesizing for Scan Dependence in Built-In Self-Testable Desings. 734-743 - Tien-Chien Lee, Niraj K. Jha, Wayne H. Wolf:
A Conditional Resource-Sharing Method for Behavior Synthesis of Highly- Testable Data Paths. 744-753 - Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal:
A Synthesis Approach to Design for Testability. 754-763
Microprocessor And VLSI Testing Case Studies
- Don Douglas Josephson, Daniel J. Dixon, Barry J. Arnold:
Test Features of the HP PA7100LC Processor. 764-772 - Rajiv Patel, Krishna Yarlagadda:
Testability Features of the SuperSPARCtm. 773-781 - Heinz Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, Reto Zimmermann, Wolfgang Fichtner:
VINCI: Secure Test of a VLSI High-Speed Encryption System. 782-790
Design-For-Test Considerations For Mixed-Signal Devices
- Eiichi Teraoka, Toru Kengaku, Ikuo Yasui, Kazuyuki Ishikawa, Takahiro Matsuo, Hideyuki Wakada, Narumi Sakashita, Yukihiko Shimazu, Takeshi Tokuda:
A Built-in Self- Test for ADC and DAC in a Single-Chip Speech CODEC. 791-796 - Ed Flaherty, Andrew Allen, John Morris:
Design for Testability of a Modular, Mixed Signal Family of VLSI Devices. 797-804 - Michael F. Toner, Gordon W. Roberts:
A BIST Scheme for an SNR Test of a Sigma-Delta ADC. 805-814
Memory Test
- Manoj Sachdev, Math Verstraelen:
Development of Fault Model and Test Algorithms for Embedded DRAMs. 815-824 - Robert P. Treuer, Vinod K. Agarwal:
Fault Location Algorithms for Repairable Embedded. 825-834 - Janusz Sosnowski:
"In System" Transparent Autodiagnostics of Rams. 835-844
Software Testing Methods
- Richard H. Carver:
Mutation-Based Testing of Concurrent Programs. 845-853 - James F. Leathrum, K. A. Liburdy:
Automated Testing of Open Software Standards. 854-858 - Anneliese von Mayrhauser, Kurt M. Olender:
Efficient Testing of Software Modifications. 859-864
Detection Of Physical Defects
- Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò:
Analyss of Dynamic Effects of Resistive Bridging Faults in CMOS and BiCMOS Digital ICs. 865-874 - Chennian Di, Jochen A. G. Jess:
On Accurate Modeling and Efficient Simulation of CMOS Opens. 875-882 - Udo Mahlstedt, Jürgen Alt:
Simulation of non-classical Faults on the Gate Level - The Fault Simulator COMISM -. 883-892
Test Engineering Strategies II
- Bryan J. Dinteman, Paul Botsford:
Differential Virtual Instrumentation with Continuously. 893-901 - Kenneth D. Wagner, Bernd Könemann:
Testable Programmable Digital Clock Pulse Control Elements. 902-909 - Himanshu Kumar, Scott A. Erjavic:
Knowledge-Based Testing. 910-917
Selected Topics In Test
- Paul Sakamoto, Tom Chiu:
High-Speed Sampling Capability for a VLSI Mixed-Signal Tester. 918-927 - Kent Kwang, Hsin Wang, Arthur Hu, Mitsuyuki Asaki, Hironobu Niijima:
CAD-Driven High-Precision E-Beam Positioning. 928-935 - Richard F. Herlein:
Terminating Transmission lines in the Test Environment. 936-944 - R. Mehtani, Bert Atzema, M. De Jonghe, Richard Morren, Geert Seuren, Taco Zwemstra:
Mix Test: A Mixed-Signal Extension to a Digital Test System. 945-953
Delay Testing
- Kwang-Ting Cheng, Hsi-Chuan Chen:
Delay Testing for Non-Robust Untestable Circuits. 954-961 - Ankan K. Pramanick, Sandip Kundu:
Design of Scan-Based Path-Delay-Testable Sequential Circuits. 962-971 - Udo Mahlstedt:
DELTEST: Deterministic Test Generation for Gate-Delay Faults. 972-980
DFT: New Tricks Of The Old Trade
- Chauchin Su, Kychin Hwang:
A Serial-Scan Test-Vector-Compression Methodology. 981-988 - Yves Bertrand, Frédéric Bancel, Michel Renovell:
Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits. 989-997 - Irith Pomeranz, Sudhakar M. Reddy:
A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test. 998-1007 - Miron Abramovici, Prashant S. Parikh, Ben Mathew, Daniel G. Saab:
On Selecting Flip-Flops for Partial Reset. 1008-1012
BIST Pattern Generation
- Danial J. Neebel, Charles R. Kime:
Inhomogeneous Cellular Automata for Weighted-Random-Pattern Generation. 1013-1022 - Miguel Miranda, Carlos A. López-Barrio:
Generation of Optimized Single Distributions of Weights for Random Built-in Self-Test. 1023-1030 - Michael Bershteyn:
Calculatoin of Multiple Sets of Weights for Weighted-Random Testing. 1031-1040 - Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer:
Novel Test Pattern Generators for Pseudo-Exhaustive Testing. 1041-1050
1992 Best Paper
- Robert C. Aitken:
BP-1992 A Comparison of Defect Models for Fault Location with IDDQ Measurements. 1051-1060
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-04 01:26 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
