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Journal Articles
- 2007
[j2]Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar:
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. Int. J. Parallel Program. 35(6): 507-527 (2007)- [j1]Anup Gangwar, M. Balakrishnan, Anshul Kumar:
Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures. ACM Trans. Design Autom. Electr. Syst. 12(1): 1:1-1:29 (2007)
Conference and Workshop Papers
- 2021
- [c8]Anup Gangwar, Ravishankar Sreedharan, Ambica Prasad, Nitin Kumar Agarwal, Sri Harsha Gade:
Topology Agnostic Virtual Channel Assignment and Protocol Level Deadlock Avoidance in a Network-on-Chip. DAC 2021: 61-66 - [c7]Sri Harsha Gade, Anup Gangwar, Ambica Prasad, Nitin Kumar Agarwal, Ravishankar Sreedharan:
An Automated Traffic Generation Framework for Performance Evaluation of Networks-on-Chip for Real World Use Cases. ISPASS 2021: 81-83 - 2020
- [c6]Anup Gangwar, Nitin Kumar Agarwal, Ravishankar Sreedharan, Ambica Prasad, Sri Harsha Gade, Zheng Xu:
Automated Synthesis of Custom Networks-on-Chip for Real World Applications. ICCAD 2020: 41:1-41:9 - 2019
- [c5]Anup Gangwar, Zheng Xu, Nitin Kumar Agarwal, Ravishankar Sreedharan, Ambica Prasad:
Traffic Driven Automated Synthesis of Network-on-Chip from Physically Aware Behavioral Specification. ISVLSI 2019: 122-127 - 2005
- [c4]Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar:
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. DATE 2005: 730-735 - [c3]Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, Subhashis Banerjee:
SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only). FPGA 2005: 273 - 2003
- [c2]Amarjeet Singh, Amit Chhabra, Anup Gangwar, Basant Kumar Dwivedi, M. Balakrishnan, Anshul Kumar:
SoC Synthesis with Automatic Hardware Software Interface Generation. VLSI Design 2003: 585- - 2002
- [c1]M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha:
A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. ISSS 2002: 2-7
Coauthor Index
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