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ORCIDFatih Kocan
Person information
- affiliation: Southern Methodist University, Dallas, Texas, USA
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2010 – 2019
- 2013
[i1]Fatih Kocan:
A nonenumerative algorithm to find the k longest (shortest) paths in a DAG. CoRR abs/1301.0181 (2013)- 2010
- [c12]Vijay K. Sirigir, Khawla Alzoubi
, Daniel G. Saab, Fatih Kocan, Massood Tabib-Azar:
Ultra-low-Power Ultra-fast Hybrid CNEMS-CMOS FPGA. FPL 2010: 368-373
2000 – 2009
- 2009
- [j7]Fatih Kocan, Lun Li, Daniel G. Saab:
Exact Path Delay Fault Coverage Calculation of Partitioned Circuits. IEEE Trans. Computers 58(6): 858-864 (2009) - 2007
- [j6]Fatih Kocan, Daniel G. Saab:
Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware. J. Electron. Test. 23(5): 405-420 (2007) - [j5]Jason Meyer, Fatih Kocan:
Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 15(2): 182-195 (2007) - [c11]Jason Meyer, Fatih Kocan, Daniel G. Saab:
Critical Path Delay Reduction in FPGAs with Unbalanced Lookup Times. ERSA 2007: 182-190 - 2005
- [j4]Fatih Kocan, Mehmet Hadi Gunes, Atakan Kurt:
On-Line Pruning of ZBDD for Path Delay Fault Coverage Calculation. IEICE Trans. Inf. Syst. 88-D(7): 1381-1388 (2005) - [j3]Fatih Kocan, Mehmet Hadi Gunes:
On the ZBDD-based nonenumerative path delay fault coverage calculation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7): 1137-1143 (2005) - [c10]Fatih Kocan, Mehmet Hadi Gunes:
Acyclic circuit partitioning for path delay fault emulation. AICCSA 2005: 22 - 2004
- [c9]Alex Fit-Florea, Miroslav Halás, Fatih Kocan:
Enhancing Reliability of Operational Interconnections in FPGAs. DATE 2004: 746-747 - [c8]Fatih Kocan, Jason Meyer:
Logic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays. FPL 2004: 289-300 - 2003
- [c7]Fatih Kocan:
Reconfigurable Randomized K-way Graph Partitioning. DSD 2003: 272-278 - [c6]Fatih Kocan:
Reconfigurable randomized K-way graph partitioning. FPGA 2003: 245 - 2002
- [j2]Fatih Kocan, Daniel G. Saab:
Correction to "ATPG for combinational circuits on configurable hardware". IEEE Trans. Very Large Scale Integr. Syst. 10(3): 374-374 (2002) - [c5]Daniel G. Saab, Fatih Kocan, Jacob A. Abraham:
Massively Parallel/Reconfigurable Emulation Model for the D-algorithm. FPL 2002: 1172-1176 - 2001
- [j1]Fatih Kocan, Daniel G. Saab:
ATPG for combinational circuits on configurable hardware. IEEE Trans. Very Large Scale Integr. Syst. 9(1): 117-129 (2001) - 2000
- [c4]Tarachand Pagarani, Fatih Kocan, Daniel G. Saab, Jacob A. Abraham:
Parallel and scalable architecture for solving SATisfiability on reconfigurable FPGA. CICC 2000: 147-150
1990 – 1999
- 1999
- [c3]Fatih Kocan, Daniel G. Saab:
Dynamic Fault Diagnosis on Reconfigurable Hardware. DAC 1999: 691-696 - [c2]Fatih Kocan, Daniel G. Saab:
Concurrent D-algorithm on reconfigurable hardware. ICCAD 1999: 152-156 - 1998
- [c1]Fatih Kocan, Daniel G. Saab:
Dynamic fault diagnosis for sequential circuits on reconfigurable hardware. ICCD 1998: 214-215
Coauthor Index
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