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ORCIDIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 24
Volume 24, Number 1, January 2005
- Andrei Radulescu, John Dielissen, Santiago González Pestana, Om Prakash Gangwal, Edwin Rijpkema, Paul Wielage, Kees Goossens:
An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration. 4-17 - Kihwan Choi, Ramakrishna Soma, Massoud Pedram:
Fine-grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off-chip access to on-chip computation times. 18-28 - Pietro Babighian, Luca Benini
, Enrico Macii:
A scalable algorithm for RTL insertion of gated clocks based on ODCs computation. 29-42 - Joel R. Phillips, Luís Miguel Silveira:
Poor man's TBR: a simple model reduction scheme. 43-55 - Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury:
ADAMIN: automated, accurate macromodeling of digital aggressors for power and ground supply noise prediction. 56-64 - Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Digital ground bounce reduction by supply current shaping and clock frequency Modulation. 65-76 - Saravanan Padmanaban, Spyros Tragoudas:
Efficient identification of (critical) testable path delay faults using decision diagrams. 77-87 - Antonis M. Paschalis, Dimitris Gizopoulos:
Effective software-based self-test strategies for on-line periodic testing of embedded processors. 88-99 - Alberto La Rosa, Luciano Lavagno, Claudio Passerone:
Implementation of a UMTS turbo decoder on a dynamically reconfigurable platform. 100-106 - Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha:
Threshold network synthesis and optimization and its application to nanotechnologies. 107-118 - Christoph Grimm, Wilhelm Heupke, Klaus Waldschmidt:
Analysis of mixed-signal systems with affine arithmetic. 118-123
Volume 24, Number 2, February 2005
- Hyeong-Ju Kang, In-Cheol Park:
SAT-based unbounded symbolic model checking. 129-140 - Le Cai, Yung-Hsiang Lu:
Energy management using buffer memory for streaming data. 141-152 - Marcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles:
Cosynthesis of energy-efficient multimode embedded systems with consideration of mode-execution probabilities. 153-169 - Guoqing Chen, Eby G. Friedman:
An RLC interconnect model based on fourier analysis. 170-183 - Peng Li, Lawrence T. Pileggi:
Compact reduced-order modeling of weakly nonlinear analog and RF circuits. 184-203 - François Pêcheux, Christophe Lallement, Alain Vachoux:
VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems. 204-225 - Ting Mei, Jaijeet S. Roychowdhury, Todd S. Coffey, Scott A. Hutchinson, David M. Day:
Robust, stable time-domain methods for solving MPDEs of fast/slow systems. 226-239 - Jiang Brandon Liu, Andreas G. Veneris:
Incremental fault diagnosis. 240-251 - Hiroshi Takahashi, Keith J. Keller, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu:
A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits. 252-263 - Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey:
Optimized reseeding by seed ordering and encoding. 264-270 - Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail:
Realizable reduction of interconnect circuits including self and mutual inductances. 271-277 - Yoonseo Choi, Taewhan Kim, Hwansoo Han:
Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design. 278-287 - Irith Pomeranz, Sudhakar M. Reddy:
On masking of redundant faults in synchronous sequential circuits with design-for-testability logic. 288-294 - A. Prasad Vinod, Edmund Ming-Kit Lai:
On the implementation of efficient channel filters for wideband receivers by optimizing common subexpression elimination methods. 295-304
Volume 24, Number 3, March 2005
- Donald Chai, Andreas Kuehlmann:
A fast pseudo-Boolean constraint solver. 305-317 - Satish Pillai, Margarida F. Jacome:
Predicated switching - optimizing speculation on EPIC machines. 318-335 - Lin Zhong, Niraj K. Jha:
Interconnect-aware low-power high-level synthesis. 336-351 - Victor Bourenkov, Kevin G. McCarthy, Alan Mathewson:
MOS table models for circuit simulation. 352-362 - Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy:
Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile. 363-381 - Jason Cong, Jie Fang, Min Xie, Yan Zhang:
MARS-a multilevel full-chip gridless routing system. 382-394 - Pongstorn Maidee, Cristinel Ababei, Kia Bazargan:
Timing-driven partitioning-based placement for island style FPGAs. 395-406 - Kai Wang, Malgorzata Marek-Sadowska:
On-chip power-supply network optimization using multigrid-based technique. 407-417 - Sheldon X.-D. Tan:
A general hierarchical circuit modeling and simulation algorithm. 418-434 - Krishnendu Chakrabarty, Vikram Iyengar, Mark D. Krasniewski:
Test planning for modular testing of hierarchical SOCs. 435-448 - Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis:
Built-in sequential fault self-testing of array multipliers. 449-460 - Maged Ghoneima, Yehea I. Ismail:
Optimum positioning of interleaved repeaters in bidirectional buses. 461-469 - Suvodeep Gupta, Srinivas Katkoori:
Intrabus crosstalk estimation using word-level statistics. 469-478 - Payam Heydari, Massoud Pedram:
Capacitive coupling noise in high-speed VLSI circuits. 478-488 - Spyros Tragoudas, Vijay Nagarandal:
On-chip embedding mechanisms for large sets of vectors for delay test. 488-497
Volume 24, Number 4, April 2005
- R. Iris Bahar, Hui-Yuan Song, Kundan Nepal, Joel Grodstein:
Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing. 502-515 - Jianwen Zhu, Silvian Calman:
Context sensitive symbolic pointer analysis. 516-531 - Robert B. Reese, Mitchell A. Thornton, Cherrice Traver, David Hemmendinger:
Early evaluation for performance enhancement in phased logic. 532-550 - Jingcao Hu, Radu Marculescu:
Energy- and performance-aware mapping for regular NoC architectures. 551-562 - Bikram Baidya, Tamal Mukherjee:
Layout verification for mixed-domain integrated MEMS. 563-577 - Hung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong:
Simultaneous power supply planning and noise avoidance in floorplan design. 578-587 - Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao:
The Y architecture for on-chip interconnect: analysis and methodology. 588-599 - Sampath Dechu, Zion Cien Shen, Chris C. N. Chu:
An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations. 600-608 - Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu:
Buffer planning as an Integral part of floorplanning with consideration of routing congestion. 609-621 - Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy:
Finite memory test response compactors for embedded test applications. 622-634 - Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip. 635-645 - Ankur Srivastava, Seda Ogrenci Memik, Bo-Kyung Choi, Majid Sarrafzadeh:
On effective slack management in postscheduling phase. 645-653 - Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram:
On the numerical stability of Green's function for substrate coupling in integrated circuits. 653-658
Volume 24, Number 5, May 2005
- Mario R. Casu, Luca Macchiarulo:
Throughput-driven floorplanning with wire pipelining. 663-675 - Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar:
Early-stage power grid analysis for uncertain working modes. 676-682 - Jaskirat Singh, Sachin S. Sapatnekar:
Congestion-aware topology optimization of structured power/ground networks. 683-695 - Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang:
A predictive distributed congestion metric with application to technology mapping. 696-710 - Haoxing Ren, David Zhigang Pan, David S. Kung:
Sensitivity guided net weighting for placement-driven synthesis. 711-721 - Natarajan Viswanathan, Chris C. N. Chu:
FastPlace: efficient analytical placement using cell shifting, iterative local refinement, and a hybrid net model. 722-733 - Andrew B. Kahng, Qinke Wang:
Implementation and extensibility of an analytic placer. 734-747 - Ameya R. Agnihotri, Satoshi Ono, Chen Li, Mehmet Can Yildiz, Ateen Khatkhate, Cheng-Kok Koh, Patrick H. Madden:
Mixed block placement via fractional cut recursive bisection. 748-761 - Qinghua Liu, Malgorzata Marek-Sadowska:
A study of netlist structure and placement efficiency. 762-772 - Kai Wang, Yajun Ran, Hailin Jiang, Malgorzata Marek-Sadowska:
General skew constrained clock network sizing based on sequential linear programming. 773-782 - Rafael Escovar, Salvador Ortiz, Roberto Suaya:
An improved long distance treatment for mutual inductance. 783-793
Volume 24, Number 6, June 2005
- Yu-Min Lee, Yahong Cao, Tsung-Hao Chen, Janet Meiling Wang, Charlie Chung-Ping Chen:
HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery. 797-806 - Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller:
Toffoli network synthesis with templates. 807-817 - Davide Bertozzi, Luca Benini, Giovanni De Micheli:
Error control schemes for on-chip communication links: the energy-reliability tradeoff. 818-831 - Anand Ramachandran, Margarida F. Jacome:
Xtream-fit: an energy-delay efficient data memory subsystem for embedded media processing. 832-848 - Amir H. Ajami, Kaustav Banerjee, Massoud Pedram:
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. 849-861 - Kyu-Il Lee, Chanho Lee, Hyungsoon Shin, Young June Park, Hong-Shick Min:
Efficient frequency-domain simulation technique for short-channel MOSFET. 862-868 - Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Lee:
Crosstalk- and performance-driven multilevel full-chip routing. 869-878 - Weiping Shi, Zhuo Li:
A fast algorithm for optimal buffer insertion. 879-891 - Said Hamdioui, John Eleazar Q. Delos Reyes:
New data-background sequences and their industrial evaluation for word-oriented random-access memories. 892-904 - Mohammad Gh. Mohammad, Kewal K. Saluja:
Optimizing program disturb fault tests using defect-based testing. 905-915 - Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara:
Improving test effectiveness of scan-based BIST by scan chain partitioning. 916-927 - Jun Chen, Lei He:
Piecewise linear model for transmission line with capacitive loading and ramp input. 928-937 - Adnan Kabbani, Dhamin Al-Khalili, Asim J. Al-Khalili:
Delay analysis of CMOS gates using modified logical effort model. 937-947 - Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja:
Combinational automatic test pattern generation for acyclic sequential circuits. 948-956 - Dan Zhao, Shambhu J. Upadhyaya:
Dynamically partitioned test scheduling with adaptive TAM configuration for power-constrained SoC testing. 956-965
Volume 24, Number 7, July 2005
- Nahri Moreano, Edson Borin, Cid C. de Souza, Guido Araujo:
Efficient datapath merging for partially reconfigurable architectures. 969-980 - Zhenhai Zhu, Ben Song, Jacob K. White:
Algorithms in FastImp: a fast and wide-band impedance extraction program for complicated 3-D geometries. 981-998 - Amit Chowdhary, John P. Hayes:
Area-optimal technology mapping for field-programmable gate arrays based on lookup tables. 999-1013 - Dongwoo Lee, David T. Blaauw, Dennis Sylvester:
Static leakage reduction through simultaneous Vt/Tox and state assignment. 1014-1029 - Le Yan, Jiong Luo, Niraj K. Jha:
Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems. 1030-1041 - Weiping Liao, Lei He, Kevin M. Lepak:
Temperature and supply Voltage aware performance and power modeling at microarchitecture level. 1042-1053 - Shankar Balachandran, Dinesh Bhatia:
A priori wirelength and interconnect estimation based on circuit characteristic. 1054-1065 - Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang:
Spanning graph-based nonrectilinear steiner tree algorithms. 1066-1075 - Kavel M. Büyüksahin, Farid N. Najm:
Early power estimation for VLSI circuits. 1076-1088 - Xun Liu, Marios C. Papaefthymiou:
HyPE: hybrid power estimation for IP-based systems-on-chip. 1089-1103 - Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma:
Layout-aware scan chain synthesis for improved path delay fault coverage. 1104-1114 - Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaudhuri:
Fault diagnosis of VLSI circuits with cellular automata based pattern classifier. 1115-1131 - M. Moiz Khan, Spyros Tragoudas:
Rewiring for watermarking digital circuit netlists. 1132-1137 - Fatih Kocan, Mehmet Hadi Gunes:
On the ZBDD-based nonenumerative path delay fault coverage calculation. 1137-1143
Volume 24, Number 8, August 2005
- Darko Kirovski, Milenko Drinic, Miodrag Potkonjak:
Engineering change protocols for behavioral and system synthesis. 1145-1155 - Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail:
Weibull-based analytical waveform model. 1156-1168 - Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky, Yuhong Zheng:
Compressible area fill synthesis. 1169-1187 - Bo Hu, Malgorzata Marek-Sadowska:
Multilevel fixed-point-addition-based VLSI placement. 1188-1203 - Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar:
Power grid analysis using random walks. 1204-1224 - Xiaochun Duan, Kartikeya Mayaram:
An efficient and robust method for ring-oscillator simulation using the harmonic-balance method. 1225-1233 - Koji Ara, Kei Suzuki:
Fine-grained transaction-level verification: using a variable transactor for improved coverage at the signal level. 1234-1240 - Sheldon X.-D. Tan, Weikun Guo, Zhenyu Qi:
Hierarchical approach to exact symbolic analysis of large analog circuits. 1241-1250 - Bing Zhong, Tao Hu, Dawei Fu, Steven L. Dvorak, John L. Prince:
A study of a hybrid phase-pole macromodel for transient simulation of complex interconnects structures. 1250-1261 - Hiren D. Patel, Sandeep K. Shukla:
Towards a heterogeneous simulation kernel for system-level models: a SystemC kernel for synchronous data flow models. 1261-1271 - Irith Pomeranz, Sudhakar M. Reddy:
On fault equivalence, fault dominance, and incompletely specified test sets. 1271-1274 - Jun Chen, Lei He:
Worst case crosstalk noise for nonswitching victims in high-speed buses. 1275-1283 - Hao Yu, Lei He:
A provably passive and cost-efficient model for inductive interconnects. 1283-1294 - Xiaoming Yu, Miron Abramovici:
Sequential circuit ATPG using combinational algorithms. 1294-1310
Volume 24, Number 9, September 2005
- Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Delay-fault diagnosis using timing information. 1315-1325 - Valeriy Sukharev:
Physically based simulation of electromigration-induced degradation mechanisms in dual-inlaid copper interconnects. 1326-1335 - Medha Kulkarni, Tom Chen:
A sensitivity-based approach to analyzing signal delay uncertainty of coupled interconnects. 1336-1346 - Jianwen Zhu, Fang Fang, Qianying Tang:
Calligrapher: a new layout-migration engine for hard intellectual property libraries. 1347-1361 - Man Lung Mui, Kaustav Banerjee, Amit Mehrotra:
Supply and power optimization in leakage-dominant technologies. 1362-1371 - Manidip Sengupta, Sharad Saxena, Lidia Daldoss, Glen Kramer, Sean Minehane, Jianjun Cheng:
Application-specific worst case corners using response surfaces and statistical models. 1372-1380 - Carl-Johan H. Seger, Robert B. Jones, John W. O'Leary, Thomas F. Melham, Mark D. Aagaard, Clark W. Barrett, Don Syme:
An industrially effective environment for formal hardware verification. 1381-1405 - Yajun Ran, Alex Kondratyev, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska:
Eliminating false positives in crosstalk noise analysis. 1406-1419 - Shu Yan, Vivek Sarin, Weiping Shi:
Sparse transformations and preconditioners for 3-D capacitance extraction. 1420-1426 - Hao Gang Wang, Chi Hou Chan, Leung Tsang:
A new multilevel Green's function interpolation method for large-scale low-frequency EM simulations. 1427-1443 - Young-Su Kwon, Chong-Min Kyung:
Performance-driven event-based synchronization for multi-FPGA simulation accelerator with event time-multiplexing bus. 1444-1456 - Dhiraj K. Pradhan, Chunsheng Liu:
EBIST: a novel test generator with built-in fault detection capability. 1457-1466 - Hongliang Chang, Sachin S. Sapatnekar:
Statistical timing analysis under spatial correlations. 1467-1482
Volume 24, Number 10, October 2005
- Clemens Heitzinger, Alireza Sheikholeslami, Jong Mun Park, Siegfried Selberherr:
A method for generating structurally aligned grids for semiconductor device simulation. 1485-1491 - Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe:
Quasi-static scheduling of independent tasks for reactive systems. 1492-1514 - Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler:
Combining ordered best-first search with branch and bound for exact BDD minimization. 1515-1529 - Dongkun Shin, Jihong Kim:
Intra-task voltage scheduling on DVS-enabled hard real-time systems. 1530-1549 - Tatjana V. Pesic, Nebojsa D. Jankovic:
A compact nonquasi-static MOSFET model based on the equivalent nonlinear transmission line. 1550-1561 - Rong Jiang, Wenyin Fu, Charlie Chung-Ping Chen:
EPEEC: comprehensive SPICE-compatible reluctance extraction for high-speed interconnects above lossy multilayer substrates. 1562-1571 - Kenneth Eguro, Scott Hauck:
Resource allocation for coarse-grain FPGA development. 1572-1581 - Soumitra Bose, Amit Nandi:
Schematic array models for associative and non-associative memory circuits. 1582-1593 - Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy:
On reducing test application time for scan circuits using limited scan operations and transfer sequences. 1594-1605 - Alexander Smith, Andreas G. Veneris, Moayad Fahim Ali, Anastasios Viglas:
Fault diagnosis and logic debugging using Boolean satisfiability. 1606-1621 - Hsu-Wei Huang, Cheng-Yeh Wang, Jing-Yang Jou:
An efficient heterogeneous tree multiplexer synthesis technique. 1622-1629 - Gethin Norman, David Parker, Marta Z. Kwiatkowska, Sandeep K. Shukla:
Evaluating the reliability of NAND multiplexing with PRISM. 1629-1637 - Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili:
Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree. 1637-1643
Volume 24, Number 11, November 2005
- Shinobu Nagayama, Tsutomu Sasao:
On the optimization of heterogeneous MDDs. 1645-1659 - Federico Angiolini, Luca Benini, Alberto Caprara:
An efficient profile-based algorithm for scratchpad memory partitioning. 1660-1676 - Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
Input space-adaptive optimization for embedded-software synthesis. 1677-1693 - Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Generation of distributed logic-memory architectures through high-level synthesis. 1694-1711 - Fei Li, Yizhou Lin, Lei He, Deming Chen, Jason Cong:
Power modeling and characteristics of field programmable gate arrays. 1712-1724 - Dinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen:
Modeling delay and noise in arbitrarily coupled RC trees. 1725-1739 - Bo Yang, Ramesh Karri, David A. McGrew:
Divide-and-concatenate: an architecture-level optimization technique for universal hash functions. 1740-1747 - Chien-Mo James Li, Edward J. McCluskey:
Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs. 1748-1759 - Haralampos-G. D. Stratigopoulos, Yiorgos Makris:
Nonlinear decision boundaries for testing analog circuits. 1760-1773 - Mehdi Baradaran Tahoori, Subhasish Mitra:
Application-independent testing of FPGA interconnects. 1774-1783 - Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David T. Blaauw:
Probability distribution of signal arrival times using Bayesian networks. 1784-1794 - Ken Tseng, Mark Horowitz:
False coupling exploration in timing analysis. 1795-1805
Volume 24, Number 12, December 2005
- Ivan Augé, Frédéric Pétrot, François Donnet, Pascal Gomez:
Platform-based design from parallel C specifications. 1811-1826 - Lin Yuan, Gang Qu:
Analysis of energy reduction on dynamic voltage scaling-enabled systems. 1827-1837 - Lihong Feng, Evgenii B. Rudnyi, Jan G. Korvink:
Preserving the film coefficient as a parameter in the compact thermal model for fast electrothermal simulation. 1838-1847 - Joon-Ho Lee, Qing Huo Liu:
An efficient 3-D spectral-element method for Schrödinger equation in nanodevice simulation. 1848-1858 - Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy:
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. 1859-1880 - Mariam Momenzadeh, Jing Huang, Mehdi Baradaran Tahoori, Fabrizio Lombardi:
Characterization, test, and logic synthesis of and-or-inverter (AOI) gate design for QCA implementation. 1881-1893 - Qiang Xu, Nicola Nicolici:
Modular SOC testing with reduced wrapper count. 1894-1908 - Sandip Kundu, Sujit T. Zachariah, Yi-Shing Chang, Chandra Tirumurti:
On modeling crosstalk faults. 1909-1915 - Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng:
Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets. 1915-1924 - Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi:
Longest-path selection for delay test under process variation. 1924-1929 - Patrick Schaumont, David Hwang, Ingrid Verbauwhede:
Platform-based design for an embedded-fingerprint-authentication device. 1929-1936 - A. Prasad Vinod, Edmund Ming-Kit Lai:
An efficient coefficient-partitioning algorithm for realizing low-complexity digital filters. 1936-1946
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