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ORCIDWayne Luk
Publications
- 2025
[c500]Zhiqiang Que
, Hongxiang Fan, Gabriel F. Figueiredo, Ce Guo, Wayne Luk, Ryota Yasudo, Masato Motomura:
Trustworthy Deep Learning Acceleration with Customizable Design Flow Automation. HEART 2025: 1-13- [i40]Zhiqiang Que, José Gabriel F. Coutinho, Ce Guo, Hongxiang Fan, Wayne Luk:
MetaML-Pro: Cross-Stage Design Flow Automation for Efficient Deep Learning Acceleration. CoRR abs/2502.05850 (2025) - [i33]Chang Sun, Zhiqiang Que, Vladimir Loncar, Wayne Luk, Maria Spiropulu:
da4ml: Distributed Arithmetic for Real-time Neural Networks on FPGAs. CoRR abs/2507.04535 (2025) - 2024
- [j154]Zhiqiang Que, Minghao Zhang, Hongxiang Fan, He Li, Ce Guo, Wayne Luk:
Low Latency Variational Autoencoder on FPGAs. IEEE J. Emerg. Sel. Topics Circuits Syst. 14(2): 323-333 (2024) - [j152]Patrick Odagiu, Zhiqiang Que, Javier M. Duarte, Johannes Haller, Gregor Kasieczka, Artur Lobanov, Vladimir Loncar, Wayne Luk, Jennifer Ngadiuba, Maurizio Pierini, Philipp Rincke, Arpita Seksaria, Sioni Summers, Andre Sznajder, Alexander D. Tapper, Thea Klæboe Årrestad:
Ultrafast jet classification at the HL-LHC. Mach. Learn. Sci. Technol. 5(3): 35017 (2024) - [j150]Zhiqiang Que, Hongxiang Fan, Marcus Loo, He Li, Michaela Blott, Maurizio Pierini, Alexander D. Tapper, Wayne Luk:
LL-GNN: Low Latency Graph Neural Networks on FPGAs for High Energy Physics. ACM Trans. Embed. Comput. Syst. 23(2): 17:1-17:28 (2024) - [c489]Qianzhou Wang, Zhiqiang Que, Wayne Luk:
Trustworthy Codesign by Verifiable Transformations. ITC-Asia 2024: 1-6 - [i32]Patrick Odagiu, Zhiqiang Que, Javier M. Duarte, Johannes Haller, Gregor Kasieczka, Artur Lobanov, Vladimir Loncar, Wayne Luk, Jennifer Ngadiuba, Maurizio Pierini, Philipp Rincke, Arpita Seksaria, Sioni Summers, Andre Sznajder, Alexander D. Tapper, Thea Klæboe Årrestad:
Sets are all you need: Ultrafast jet classification on FPGAs for HL-LHC. CoRR abs/2402.01876 (2024) - 2023
- [j142]Hongxiang Fan, Shuanglong Liu, Zhiqiang Que, Xinyu Niu, Wayne Luk:
High-Performance Acceleration of 2-D and 3-D CNNs on FPGAs Using Static Block Floating Point. IEEE Trans. Neural Networks Learn. Syst. 34(8): 4473-4487 (2023) - [j140]Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, He Li, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk:
Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 16(1): 4:1-4:26 (2023) - [c486]Hongxiang Fan, Mark Chen, Liam Castelli, Zhiqiang Que, He Li, Kenneth Long, Wayne Luk:
When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA. DAC 2023: 1-6 - [c483]Zhiqiang Que, Shuo Liu, Markus Rognlien, Ce Guo, José Gabriel F. Coutinho, Wayne Luk:
MetaML: Automating Customizable Cross-Stage Design-Flow for Deep Learning Acceleration. FPL 2023: 248-252 - [c482]Philippos Papaphilippou, Zhiqiang Que, Wayne Luk:
Efficiently Removing Sparsity for High-Throughput Stream Processing. ICFPT 2023: 244-249 - [i23]Zhiqiang Que, Shuo Liu, Markus Rognlien, Ce Guo, José Gabriel F. Coutinho, Wayne Luk:
MetaML: Automating Customizable Cross-Stage Design-Flow for Deep Learning Acceleration. CoRR abs/2306.08746 (2023) - [i22]Hongxiang Fan, Hao Chen, Liam Castelli, Zhiqiang Que, He Li, Kenneth Long, Wayne Luk:
When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA. CoRR abs/2308.06849 (2023) - 2022
- [j137]Hongxiang Fan, Martin Ferianc, Zhiqiang Que, Shuanglong Liu, Xinyu Niu, Miguel R. D. Rodrigues, Wayne Luk:
FPGA-Based Acceleration for Bayesian Convolutional Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5343-5356 (2022) - [j134]Hongxiang Fan, Martin Ferianc, Zhiqiang Que, Xinyu Niu, Miguel R. D. Rodrigues, Wayne Luk:
Accelerating Bayesian Neural Networks via Algorithmic and Hardware Optimizations. IEEE Trans. Parallel Distributed Syst. 33(12): 3387-3399 (2022) - [j132]Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Andrew Boutros, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Wayne Luk:
Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 30(2): 227-237 (2022) - [c478]Zhiqiang Que, Marcus Loo, Wayne Luk:
Reconfigurable Acceleration of Graph Neural Networks for Jet Identification in Particle Physics. AICAS 2022: 202-205 - [c477]Markus Rognlien, Zhiqiang Que, José Gabriel F. Coutinho, Wayne Luk:
Hardware-Aware Optimizations for Deep Learning Inference on Edge Devices. ARC 2022: 118-133 - [c475]Hongxiang Fan, Martin Ferianc, Zhiqiang Que, He Li, Shuanglong Liu, Xinyu Niu, Wayne Luk:
Algorithm and Hardware Co-design for Reconfigurable CNN Accelerator. ASP-DAC 2022: 250-255 - [c468]Zhiqiang Que, Marcus Loo, Hongxiang Fan, Maurizio Pierini, Alexander D. Tapper, Wayne Luk:
Optimizing Graph Neural Networks for Jet Tagging in Particle Physics on FPGAs. FPL 2022: 327-333 - [c467]Filip Wojcicki, Zhiqiang Que, Alexander D. Tapper, Wayne Luk:
Accelerating Transformer Neural Networks on FPGAs for High Energy Physics Experiments. FPT 2022: 1-8 - [c466]Qianzhou Wang, Yat Wong, Zhiqiang Que, Wayne Luk:
Verifying Hardware Optimizations for Efficient Acceleration. HEART 2022: 17-23 - [c462]Ziwei Wang, Zhiqiang Que, Wayne Luk, Hongxiang Fan:
Customizable FPGA-based Accelerator for Binarized Graph Neural Networks. ISCAS 2022: 1968-1972 - [i20]Zhiqiang Que, Marcus Loo, Hongxiang Fan, Michaela Blott, Maurizio Pierini, Alexander D. Tapper, Wayne Luk:
LL-GNN: Low Latency Graph Neural Networks on FPGAs for Particle Detectors. CoRR abs/2209.14065 (2022) - 2021
- [j130]Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Xinyu Niu, Steven J. E. Wilton, Wayne Luk:
In-circuit tuning of deep learning designs. J. Syst. Archit. 118: 102198 (2021) - [c459]Zhiqiang Que, Erwei Wang, Umar Marikar, Eric A. Moreno, Jennifer Ngadiuba, Hamza Javed, Bartlomiej Borzyszkowski, Thea Aarrestad, Vladimir Loncar, Sioni Summers, Maurizio Pierini, Peter Y. K. Cheung, Wayne Luk:
Accelerating Recurrent Neural Networks for Gravitational Wave Experiments. ASAP 2021: 117-124 - [c456]Daniel Holanda Noronha, Zhiqiang Que, Wayne Luk, Steven J. E. Wilton:
Flexible Instrumentation for Live On-Chip Debug of Machine Learning Training on FPGAs. FCCM 2021: 20-28 - [c451]Martin Ferianc, Zhiqiang Que, Hongxiang Fan, Wayne Luk, Miguel Rodrigues:
Optimizing Bayesian Recurrent Neural Networks on an FPGA-based Accelerator. FPT 2021: 1-10 - [i18]Martin Ferianc, Zhiqiang Que, Hongxiang Fan, Wayne Luk, Miguel Rodrigues:
High-Performance FPGA-based Accelerator for Bayesian Recurrent Neural Networks. CoRR abs/2106.06048 (2021) - [i16]Zhiqiang Que, Erwei Wang, Umar Marikar, Eric A. Moreno, Jennifer Ngadiuba, Hamza Javed, Bartlomiej Borzyszkowski, Thea Aarrestad, Vladimir Loncar, Sioni Summers, Maurizio Pierini, Peter Y. K. Cheung, Wayne Luk:
Accelerating Recurrent Neural Networks for Gravitational Wave Experiments. CoRR abs/2106.14089 (2021) - [i15]Hongxiang Fan, Martin Ferianc, Zhiqiang Que, He Li, Shuanglong Liu, Xinyu Niu, Wayne Luk:
Algorithm and Hardware Co-design for Reconfigurable CNN Accelerator. CoRR abs/2111.12787 (2021) - 2020
- [j122]Zhiqiang Que, Yongxin Zhu, Hongxiang Fan, Jiuxi Meng, Xinyu Niu, Wayne Luk:
Mapping Large LSTMs to FPGAs with Weight Reuse. J. Signal Process. Syst. 92(9): 965-979 (2020) - [c440]Hiroki Nakahara, Zhiqiang Que, Wayne Luk:
High-Throughput Convolutional Neural Network on an FPGA by Customized JPEG Compression. FCCM 2020: 1-9 - [c439]Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Xinyu Niu, Wayne Luk:
Optimizing Reconfigurable Recurrent Neural Networks. FCCM 2020: 10-18 - [c436]Hiroki Nakahara, Zhiqiang Que, Akira Jinguji, Wayne Luk:
R2CNN: Recurrent Residual Convolutional Neural Network on FPGA. FPGA 2020: 319 - [c433]Hongxiang Fan, Martin Ferianc, Shuanglong Liu, Zhiqiang Que, Xinyu Niu, Wayne Luk:
Optimizing FPGA-Based CNN Accelerator Using Differentiable Neural Architecture Search. ICCD 2020: 465-468 - [c432]Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk:
A Reconfigurable Multithreaded Accelerator for Recurrent Neural Networks. FPT 2020: 20-28 - [c427]Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Xinyu Niu, Steven J. E. Wilton, Wayne Luk:
Towards Overlay-based Rapid In-Circuit Tuning of Deep Learning Designs. FPT 2020: 301 - 2019
- [c423]Hongxiang Fan, Cheng Luo, Chenglong Zeng, Martin Ferianc, Zhiqiang Que, Shuanglong Liu, Xinyu Niu, Wayne Luk:
F-E3D: FPGA-based Acceleration of an Efficient 3D Convolutional Neural Network for Human Action Recognition. ASAP 2019: 1-8 - [c422]Zhiqiang Que, Thomas Nugent, Shuanglong Liu, Li Tian, Xinyu Niu, Yongxin Zhu, Wayne Luk:
Efficient Weight Reuse for Large LSTMs. ASAP 2019: 17-24 - [c411]Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Steven J. E. Wilton, Wayne Luk:
Towards In-Circuit Tuning of Deep Learning Designs. ICCAD 2019: 1-6 - [c408]Daniel Holanda Noronha, Ruizhe Zhao, Zhiqiang Que, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton:
An Overlay for Rapid FPGA Debug of Machine Learning Applications. FPT 2019: 135-143 - [c406]Zhiqiang Que, Yanyang Liu, Ce Guo, Xinyu Niu, Yongxin Zhu, Wayne Luk:
Real-Time Anomaly Detection for Flight Testing Using AutoEncoder and LSTM. FPT 2019: 379-382 - 2018
- [c394]Hongxiang Fan, Ho-Cheung Ng, Shuanglong Liu, Zhiqiang Que, Xinyu Niu, Wayne Luk:
Reconfigurable Acceleration of 3D-CNNs for Human Action Recognition with Block Floating-Point Representation. FPL 2018: 287-294 - [c392]Hongxiang Fan, Shuanglong Liu, Martin Ferianc, Ho-Cheung Ng, Zhiqiang Que, Shen Liu, Xinyu Niu, Wayne Luk:
A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA. FPT 2018: 14-21 - [c391]Shuanglong Liu, Chenglong Zeng, Hongxiang Fan, Ho-Cheung Ng, Jiuxi Meng, Zhiqiang Que, Xinyu Niu, Wayne Luk:
Memory-Efficient Architecture for Accelerating Generative Networks on FPGA. FPT 2018: 30-37 - [c383]Jiajun Gao, Yongxin Zhu, Meikang Qiu, Kuen Hung Tsoi, Xinyu Niu, Wayne Luk, Ruizhe Zhao, Zhiqiang Que, Wei Mao, Can Feng, Xiaowen Zha, Guobao Deng, Jiayi Chen, Tao Liu:
Reconfigurable Hardware Generation for Tensor Flow Models of CNN Algorithms on a Heterogeneous Acceleration Platform. SmartCom 2018: 87-96
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