"A 54.61-GOPS 96.35-mW Digital Logic Accelerator For Underwater Object ..."

Chua-Chin Wang et al. (2024)

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DOI: 10.1109/AICAS59952.2024.10595977

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type: Conference or Workshop Paper

metadata version: 2025-03-03

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Chua-Chin Wang, Shih-Heng Luo, Hsin-Che Wu, Ralph Gerard B. Sangalang, Chewnpu Jou, Harry Hsia, Lan-Chou Cho:
A 54.61-GOPS 96.35-mW Digital Logic Accelerator For Underwater Object Recognition DNN Using 40-nm CMOS Process. AICAS 2024: 85-89

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