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"Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications."

Ramy N. Tadros et al. (2016)

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DOI: 10.1109/ASYNC.2016.16

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  dblp key:
  - conf/async/TadrosHGMCB16
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  persistent URL:
  - https://dblp.org/rec/conf/async/TadrosHGMCB16
Ramy N. Tadros, Weizhe Hua, Matheus Gibiluka, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel:
Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications. ASYNC 2016: 11-18

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