"A Time-Area-Power Efficient Multiplier and Square Architecture Based on ..."

Himanshu Thapliyal, Hamid R. Arabnia (2004)

> Home

Details and statistics

DOI: —

access: unavailable

type: Conference or Workshop Paper

metadata version: 2004-11-23

- no documents available
- export record
  dblp key:
  - conf/csreaESA/ThapliyalA04a
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/csreaESA/ThapliyalA04a
Himanshu Thapliyal, Hamid R. Arabnia:
A Time-Area-Power Efficient Multiplier and Square Architecture Based on Ancient Indian Vedic Mathematics. ESA/VLSI 2004: 434-439

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.