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"Test configuration minimization for the logic cells of SRAM-based FPGAs: a ..."

Michel Renovell et al. (1999)

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DOI: 10.1109/ETW.1999.804520

access: closed

type: Conference or Workshop Paper

metadata version: 2021-12-24

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Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study. ETW 1999: 146-151

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