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ORCIDETW 1999: Constance, Germany
- 4th European Test Workshop, ETW 1999, Constance, Germany, May 25-28, 1999. IEEE Computer Society 1999, ISBN 0-7695-0390-X
- Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian:
A high-level EDA environment for the automatic insertion of HD-BIST structures. 2-6 - Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault:
On calculating efficient LFSR seeds for built-in self test. 7-14 - A. Schubert, Walter Anheier:
On random pattern testability of cryptographic VLSI cores. 15-20 - Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand:
Functional and structural testing of switched-current circuits. 22-27 - R. H. Beurze, Y. Xing, R. van Kleef, Ronald J. W. T. Tangelder, Nur Engin:
Practical implementation of defect-oriented testing for a mixed-signal class-D amplifier. 28-33 - Fang Xu:
A new approach for the nonlinearity test of ADCs/DACs and its application for BIST. 34-38 - Toshiyuki Maeda, Kozo Kinoshita:
Compaction of IDDQ test sequence using reassignment method. 40-45 - Rodrigo Picos, Miquel Roca, Eugeni Isern, Jaume Segura, Eugenio García-Moreno:
Experimental results on BIC sensors for transient current testing. 46-50 - Hans A. R. Manhaeve, Johan Verfaillie, B. Straka, J. P. Cornil:
Application of supply current testing to analogue circuits, towards a structural analogue test methodology. 51-56 - Sheng-Jer Kuo, Chung Len Lee, Soon-Jyh Chang, Jwu E. Chen:
A DFT for semi-DC fault diagnosis for switched-capacitor circuits. 58-63 - Salvador Mir, Benoît Charlot, Bernard Courtois:
Extending fault-based testing to microelectromechanical systems. 64-68 - Erik Jan Marinissen
, Maurice Lousberg:
The role of test protocols in testing embedded-core-based system ICs. 70-75 - Harald P. E. Vranken:
Debug facilities in the TriMedia CPU64 architecture. 76-81 - Jaan Raik, Raimund Ubar:
High-level path activation technique to speed up sequential circuit test generation. 84-89 - Irith Pomeranz, Sudhakar M. Reddy:
On avoiding undetectable faults during test generation. 90-95 - Martin Keim, Ilia Polian, Harry Hengster, Bernd Becker:
A scalable BIST architecture for delay faults. 98-103 - Marie-Lise Flottes, Christian Landrault, A. Petitqueux:
Partial set for flip-flops based on state requirement for non-scan BIST scheme. 104-109 - Gundolf Kiefer, Hans-Joachim Wunderlich:
Deterministic BIST with partial scan. 110-116 - Bernd Straube, Kurt Reinschke, Wolfgang Vermeiren, Klaus Röbenack, Bert Müller, Christoph Clauß:
On the fault-injection-caused increase of the DAE-index in analogue fault simulation. 118-122 - Anna Maria Brosa, Joan Figueras:
On maximizing the coverage of catastrophic and parametric faults. 123-128 - Gustavo Ribeiro Alves, José Manuel Martins Ferreira:
Using the BS register for capturing and storing n-bit sequences in real-time. 130-135 - Octávio Páscoa Dias, Jorge Semião, Marcelino B. Santos, Isabel Maria Cacho Teixeira, João Paulo Teixeira:
From system level to defect-oriented test: a case study. 136-141 - Peter Muhmenthaler:
Cost effective testing of systems on silicon: areas for optimization. 142-143 - Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study. 146-151 - Abderrahim Doumar, Toshiaki Ohmameuda, Hideo Ito:
Design of an automatic testing for FPGAs. 152-157 - Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
A new BIST architecture for low power circuits. 160-164 - Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos:
Low power BIST by filtering non-detecting vectors. 165-170
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