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"Improving Security of SDDL Designs through Interleaved Placement on Xilinx ..."
Rajesh Velegalati, Jens-Peter Kaps (2011)
- Rajesh Velegalati, Jens-Peter Kaps:

Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs. FPL 2011: 506-511

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