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ORCIDRajesh Velegalati
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2020 – today
- 2023
[c8]Sohrab Aftabjahani, Mark M. Tehranipoor, Farimah Farahmandi, Bulbul Ahmed, Ryan Kastner, Francesco Restuccia, Andres Meza, Kaki Ryan, Nicole Fern, Jasper Van Woudenberg, Rajesh Velegalati, Cees-Bart Breunesse, Cynthia Sturton, Calvin Deutschbein:
Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance. VTS 2023: 1-10
2010 – 2019
- 2013
- [c7]Rajesh Velegalati, Kinjal Shah, Jens-Peter Kaps:
Glitch Detection in Hardware Implementations on FPGAs Using Delay Based Sampling Techniques. DSD 2013: 947-954 - 2012
- [c6]Benjamin Y. Brewster, Ekawat Homsirikamol, Rajesh Velegalati, Kris Gaj:
Option space exploration using distributed computing for efficient benchmarking of FPGA cryptographic modules. FPT 2012: 113-118 - 2011
- [c5]Rajesh Velegalati, Jens-Peter Kaps:
Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs. FPL 2011: 506-511 - 2010
- [c4]Jens-Peter Kaps, Rajesh Velegalati:
DPA Resistant AES on FPGA Using Partial DDL. FCCM 2010: 273-280 - [c3]Rajesh Velegalati, Jens-Peter Kaps:
Techniques to enable the use of Block RAMs on FPGAS with Dynamic and Differential Logic. ICECS 2010: 1244-1247 - [c2]Shaunak Shah, Rajesh Velegalati, Jens-Peter Kaps, David Hwang:
Investigation of DPA Resistance of Block RAMs in Cryptographic Implementations on FPGAs. ReConFig 2010: 274-279
2000 – 2009
- 2009
- [c1]Rajesh Velegalati, Jens-Peter Kaps:
DPA resistance for light-weight implementations of cryptographic algorithms on FPGAs. FPL 2009: 385-390
Coauthor Index
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