"Design Flow of Accelerating Hybrid Extremely Low Bit-Width Neural Network ..."

Junsong Wang et al. (2018)

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DOI: 10.1109/FPL.2018.00035

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - https://dblp.org/rec/conf/fpl/WangLZZLC18
Junsong Wang, Qiuwen Lou, Xiaofan Zhang, Chao Zhu, Yonghua Lin, Deming Chen:
Design Flow of Accelerating Hybrid Extremely Low Bit-Width Neural Network in Embedded FPGA. FPL 2018: 163-169

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