"Design Automation Methodology from RTL to Gate-level Netlist and Schematic ..."

Rongliang Fu et al. (2020)

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DOI: 10.1145/3386263.3406898

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type: Conference or Workshop Paper

metadata version: 2025-01-19

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Rongliang Fu, Zhimin Zhang, Guang-Ming Tang, Junying Huang, Xiaochun Ye, Dongrui Fan, Ninghui Sun:
Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits. ACM Great Lakes Symposium on VLSI 2020: 145-150

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