"A 0.7 μm CMOS clock recovery circuit for 622 Mb/s SDH systems."

Eduardo de Vasconcelos, Rui L. Aguiar, Dinis M. Santos (1998)

> Home

Details and statistics

DOI: 10.1109/ICECS.1998.814019

access: closed

type: Conference or Workshop Paper

metadata version: 2021-08-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/icecsys/VasconcelosAS98
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/icecsys/VasconcelosAS98
Eduardo de Vasconcelos, Rui L. Aguiar, Dinis M. Santos:
A 0.7 μm CMOS clock recovery circuit for 622 Mb/s SDH systems. ICECS 1998: 411-414

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.