"Improved 3D DRAM Design Based on Gate-Controlled Thyristor Featuring Two ..."

Wei-Chen Chen et al. (2024)

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DOI: 10.1109/IMW59701.2024.10536917

access: closed

type: Conference or Workshop Paper

metadata version: 2024-06-10

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Wei-Chen Chen, Hang-Ting Lue, Ming-Hung Wu, Yu-Tang Lin, Keh-Chung Wang, Chih-Yuan Lu:
Improved 3D DRAM Design Based on Gate-Controlled Thyristor Featuring Two Asymmetrical Horizontal WL's and Vertical BL for Better Cell Size Scaling and Array Selection. IMW 2024: 1-4

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