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"A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ..."

Seung-Jun Bae et al. (2008)

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DOI: 10.1109/ISSCC.2008.4523165

access: closed

type: Conference or Workshop Paper

metadata version: 2021-06-29

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  dblp key:
  - conf/isscc/BaeSPKCKKPLBLPKKKSPMYKLYJCJK08
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  persistent URL:
  - https://dblp.org/rec/conf/isscc/BaeSPKCKKPLBLPKKKSPMYKLYJCJK08
Seung-Jun Bae, Young-Soo Sohn, Kwang-Il Park, Kyoung-Ho Kim, Dae-Hyun Chung, Jingook Kim, Si-Hong Kim, Min-Sang Park, Jae-Hyung Lee, Sam-Young Bang, Ho-Kyung Lee, In-Soo Park, Jae-Sung Kim, Dae-Hyun Kim, Hye-Ran Kim, Yong-Jae Shin, Cheol-Goo Park, Gil-Shin Moon, Ki-Woong Yeom, Kang-Young Kim, Jae-Young Lee, Hyang-Ja Yang, Seong-Jin Jang, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim:
A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques. ISSCC 2008: 278-279

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