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"15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable ..."

Ahmed Elkholy et al. (2014)

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DOI: 10.1109/ISSCC.2014.6757431

access: closed

type: Conference or Workshop Paper

metadata version: 2020-09-05

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Ahmed Elkholy, Amr Elshazly, Saurabh Saxena, Guanghua Shu, Pavan Kumar Hanumolu:
15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS. ISSCC 2014: 272-273

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