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"Exploration and Exploitation of Dual Timing Margins for Improving Power ..."

Ning-Chi Huang, Yu-Guang Chen, Kai-Chiang Wu (2019)

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DOI: 10.1109/ISVLSI.2019.00048

access: closed

type: Conference or Workshop Paper

metadata version: 2019-09-24

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  dblp key:
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Ning-Chi Huang, Yu-Guang Chen, Kai-Chiang Wu:
Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs. ISVLSI 2019: 218-223

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