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2020 – today
- 2024
[j14]Shiuhpyng Winston Shieh
, Jeffrey M. Voas, Phil Laplante, Jason W. Rupe, Christian K. Hansen, Yu-Sung Wu, Yi-Ting Chen, Chi-Yu Li, Kai-Chiang Wu:
Reliability Engineering in a Time of Rapidly Converging Technologies. IEEE Trans. Reliab. 73(1): 73-82 (2024)- [c43]Ning-Chi Huang, Chi-Chih Chang, Wei-Cheng Lin, Endri Taka, Diana Marculescu, Kai-Chiang Wu:
ELSA: Exploiting Layer-wise N: M Sparsity for Vision Transformer Acceleration. CVPR Workshops 2024: 8006-8015 - [c42]Yu-Chen Hsiao, Chia-Heng Yen, Bo-Yang Ke, Kai-Chiang Wu:
Synergizing GCN and GAT for Hardware Trojan Detection and Localization. DSN-S 2024: 161-162 - [c41]Cheng-Che Lu, Chi-Chih Chang, Chia-Heng Yen, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu, Mango Chia-Tso Chao:
Transformer and Its Variants for Identifying Good Dice in Bad Neighborhoods. VTS 2024: 1-7 - [c40]Chi-Chih Chang, Yuan-Yao Sung, Shixing Yu, Ning-Chi Huang, Diana Marculescu, Kai-Chiang Wu:
FLORA: Fine-grained Low-Rank Architecture Search for Vision Transformer. WACV 2024: 2470-2479 - [i7]Chi-Chih Chang, Wei-Cheng Lin, Chien-Yu Lin, Chong-Yan Chen, Yu-Fang Hu, Pei-Shuo Wang, Ning-Chi Huang, Luis Ceze, Kai-Chiang Wu:
Palu: Compressing KV-Cache with Low-Rank Projection. CoRR abs/2407.21118 (2024) - [i6]Ning-Chi Huang, Chi-Chih Chang, Wei-Cheng Lin, Endri Taka, Diana Marculescu, Kai-Chiang Wu:
ELSA: Exploiting Layer-wise N:M Sparsity for Vision Transformer Acceleration. CoRR abs/2409.09708 (2024) - [i5]Hung-Yueh Chiang, Chi-Chih Chang, Natalia Frumkin, Kai-Chiang Wu, Diana Marculescu:
Quamba: A Post-Training Quantization Recipe for Selective State Space Models. CoRR abs/2410.13229 (2024) - 2023
- [j13]Chia-Heng Yen, Chun-Teng Chen, Cheng-Yen Wen, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao:
CNN-Based Stochastic Regression for IDDQ Outlier Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4282-4295 (2023) - [c39]Endri Taka, Aman Arora, Kai-Chiang Wu, Diana Marculescu:
MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine. ICFPT 2023: 96-105 - [c38]Chi-Chih Chang, Wei-Cheng Lin, Pei-Shuo Wang, Sheng-Feng Yu, Yu-Chen Lu, Kuan-Cheng Lin, Kai-Chiang Wu:
Q-YOLOP: Quantization-Aware You Only Look Once for Panoptic Driving Perception. ICME Workshops 2023: 52-56 - [c37]Ning-Chi Huang, Min-Syue Yang, Ya-Chu Chang, Kai-Chiang Wu:
Decomposable Architecture and Fault Mitigation Methodology for Deep Learning Accelerators. ISQED 2023: 1-8 - [c36]Chia-Heng Yen, Jung-Che Tsai, Kai-Chiang Wu:
Using Path Features for Hardware Trojan Detection Based on Machine Learning Techniques. ISQED 2023: 1-8 - [c35]Ching-Min Liu, Chia-Heng Yen, Shu-Wen Lee, Kai-Chiang Wu, Mango Chia-Tso Chao:
Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information. ITC 2023: 357-366 - [c34]Chin-Kuan Lin, Cheng-Che Lu, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu, Mango Chia-Tso Chao:
Outlier Detection for Analog Tests Using Deep Learning Techniques. VTS 2023: 1-7 - [c33]Yu-Teng Nien, Chen-Hong Li, Pei-Yin Wu, Yung-Jheng Wang, Kai-Chiang Wu, Mango C.-T. Chao:
Test Generation for Defect-Based Faults of Scan Flip-Flops. VTS 2023: 1-7 - [i4]Chi-Chih Chang, Wei-Cheng Lin, Pei-Shuo Wang, Sheng-Feng Yu, Yu-Chen Lu, Kuan-Cheng Lin, Kai-Chiang Wu:
Q-YOLOP: Quantization-aware You Only Look Once for Panoptic Driving Perception. CoRR abs/2307.04537 (2023) - [i3]Chi-Chih Chang, Yuan-Yao Sung, Shixing Yu, Ning-Chi Huang, Diana Marculescu, Kai-Chiang Wu:
FLORA: Fine-grained Low-Rank Architecture Search for Vision Transformer. CoRR abs/2311.03912 (2023) - [i2]Endri Taka, Aman Arora, Kai-Chiang Wu, Diana Marculescu:
MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine. CoRR abs/2311.04980 (2023) - 2022
- [j12]Yu-Teng Nien, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao:
Methodology of Generating Timing-Slack-Based Cell-Aware Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 5057-5070 (2022) - [j11]Ning-Chi Huang, Chao-Wei Cheng, Kai-Chiang Wu:
Timing Variability-Aware Analysis and Optimization for Variable-Latency Designs. IEEE Trans. Very Large Scale Integr. Syst. 30(1): 81-94 (2022) - [j10]Shuo-Wen Chang, Yu-Teng Nien, Yu-Pang Hu, Kai-Chiang Wu, Chi Chun Wang, Fu-Sheng Huang, Yi-Lun Tang, Yung-Chen Chen, Ming-Chien Chen, Mango C.-T. Chao:
Test Methodology for Defect-Based Bridge Faults. IEEE Trans. Very Large Scale Integr. Syst. 30(7): 975-988 (2022) - [c32]Dong-Zhen Lee, Ying-Yen Chen, Kai-Chiang Wu, Mango C.-T. Chao:
Improving Cell-Aware Test for Intra-Cell Short Defects. DATE 2022: 436-441 - [c31]Ho-Chieh Hsu, Cheng-Che Lu, Shih-Wei Wang, Kelly Jones, Kai-Chiang Wu, Mango C.-T. Chao:
Rule Generation for Classifying SLT Failed Parts. VTS 2022: 1-7 - 2021
- [j9]Li-Wei Chen, Wei-Chun Wang, Shao-Han Ko, Chien-Yu Chen, Chih-Ting Hsu, Fu-Ching Chiao, Tse-Wei Chen, Kai-Chiang Wu, Hao-Wu Lin:
Highly Uniform All-Vacuum-Deposited Inorganic Perovskite Artificial Synapses for Reservoir Computing. Adv. Intell. Syst. 3(1): 2000196 (2021) - [j8]Li-Wei Chen, Wei-Chun Wang, Shao-Han Ko, Chien-Yu Chen, Chih-Ting Hsu, Fu-Ching Chiao, Tse-Wei Chen, Kai-Chiang Wu, Hao-Wu Lin:
Highly Uniform All-Vacuum-Deposited Inorganic Perovskite Artificial Synapses for Reservoir Computing. Adv. Intell. Syst. 3(1): 2170010 (2021) - [c30]Xiao Hu, Ming-Ching Chang, Yuwei Chen, Rahul Sridhar, Zhenyu Hu, Yunhe Xue, Zhenyu Wu, Pengcheng Pi, Jiayi Shen, Jianchao Tan, Xiangru Lian, Ji Liu, Zhangyang Wang, Chia-Hsiang Liu, Yu-Shin Han, Yuan-Yao Sung, Yi Lee, Kai-Chiang Wu, Wei-Xiang Guo, Rick Lee, Shengwen Liang, Zerun Wang, Guiguang Ding, Gang Zhang, Teng Xi, Yubei Chen, Han Cai, Ligeng Zhu, Zhekai Zhang, Song Han, Seonghwan Jeong, YoungMin Kwon, Tianzhe Wang, Jeffery Pan:
The 2020 Low-Power Computer Vision Challenge. AICAS 2021: 1-4 - [c29]Chia-Hsiang Liu, Yu-Shin Han, Yuan-Yao Sung, Yi Lee, Hung-Yueh Chiang, Kai-Chiang Wu:
FOX-NAS: Fast, On-device and Explainable Neural Architecture Search. ICCVW 2021: 789-797 - [c28]Samuel Liu, Jen-Ho Kuo, Luba Tang, Ning-Chi Huang, Der-Yu Tsai, M.-H. Yang, Kai-Chiang Wu:
ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design. VLSI-DAT 2021: 1-7 - [c27]Ning-Chi Huang, Wei-Kai Tseng, Huan-Jan Chou, Kai-Chiang Wu:
An Energy-Efficient Approximate Systolic Array Based on Timing Error Prediction and Prevention. VTS 2021: 1-7 - [c26]Cheng-Hao Yang, Chia-Heng Yen, Ting-Rui Wang, Chun-Teng Chen, Mason Chern, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao:
Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks. VTS 2021: 1-7 - [i1]Chia-Hsiang Liu, Yu-Shin Han, Yuan-Yao Sung, Yi Lee, Hung-Yueh Chiang, Kai-Chiang Wu:
FOX-NAS: Fast, On-device and Explainable Neural Architecture Search. CoRR abs/2108.08189 (2021) - 2020
- [j7]Tien-Hung Tseng, Chung-Han Chou, Kai-Chiang Wu:
Making Aging Useful by Recycling Aging-induced Clock Skew. ACM Trans. Design Autom. Electr. Syst. 25(2): 13:1-13:24 (2020) - [c25]Hao-Chun Chang, Li-An Huang, Kai-Chiang Wu, Yu-Guang Chen:
Selective Sensor Placement for Cost-Effective Online Aging Monitoring and Resilience. ISPD 2020: 95-102 - [c24]Yu-Pang Hu, Shuo-Wen Chang, Kai-Chiang Wu, Chi Chun Wang, Fu-Sheng Huang, Yi-Lun Tang, Yung-Chen Chen, Ming-Chien Chen, Mango C.-T. Chao:
Test Methodology for Defect-based Bridge Faults. ITC-Asia 2020: 106-111 - [c23]Shu-Ming Liu, Luba Tang, Ning-Chi Huang, Der-Yu Tsai, Ming-Xue Yang, Kai-Chiang Wu:
Fault-Tolerance Mechanism Analysis on NVDLA-Based Design Using Open Neural Network Compiler and Quantization Calibrator. VLSI-DAT 2020: 1-3 - [c22]Chun-Teng Chen, Chia-Heng Yen, Cheng-Yen Wen, Cheng-Hao Yang, Kai-Chiang Wu, Mason Chern, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao:
CNN-based Stochastic Regression for IDDQ Outlier Identification. VTS 2020: 1-6
2010 – 2019
- 2019
- [c21]Yun-Ting Wang, Kai-Chiang Wu, Chung-Han Chou, Shih-Chieh Chang:
Aging-aware chip health prediction adopting an innovative monitoring strategy. ASP-DAC 2019: 179-184 - [c20]Ning-Chi Huang, Szu-Ying Chen, Kai-Chiang Wu:
Sensor-Based Approximate Adder Design for Accelerating Error-Tolerant and Deep-Learning Applications. DATE 2019: 692-697 - [c19]Kai-Chiang Wu, Wei-Tao Huang, Chiao-Yang Huang:
ICE-RADAR: In-situ, Cost-Effective Razor Flip-Flop Deployment for Aging Resilience. IOLTS 2019: 263-268 - [c18]Ning-Chi Huang, Yu-Guang Chen, Kai-Chiang Wu:
Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs. ISVLSI 2019: 218-223 - [c17]Yu-Teng Nien, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao:
Methodology of Generating Timing-Slack-Based Cell-Aware Tests. ITC 2019: 1-10 - [c16]Tse-Wei Wu, Dong-Zhen Lee, Yu-Hao Huang, Mango C.-T. Chao, Kai-Chiang Wu, Shu-Yi Kao, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee:
Layout-Based Dual-Cell-Aware Tests. VTS 2019: 1-6 - 2018
- [j6]Chung-Han Chou, Tsui-Yun Chang, Kai-Chiang Wu, Shih-Chieh Chang:
Sensor-Based Time Speculation in the Presence of Timing Variability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1133-1142 (2018) - [c15]Tien-Hung Tseng, Shou-Chun Li, Kai-Chiang Wu:
Lifetime Reliability Trojan Based on Exploring Malicious Aging. ATS 2018: 74-79 - [c14]Kai-Chiang Wu, Tien-Hung Tseng, Shou-Chun Li:
MAUI: Making aging useful, intentionally. DATE 2018: 527-532 - 2017
- [c13]Chang-Lin Tsai, Chao-Wei Cheng, Ning-Chi Huang, Kai-Chiang Wu:
Analysis and optimization of variable-latency designs in the presence of timing variability. DATE 2017: 1219-1224 - [c12]Tien-Hung Tseng, Shu-Sheng Wang, Jian-You Chen, Kai-Chiang Wu:
Workload-aware lifetime Trojan based on statistical aging manipulation. DSC 2017: 159-165 - [c11]Kao-Chi Lee, Kai-Chiang Wu, Chih-Ying Tsai, Mango Chia-Tso Chao:
Fast WAT test structure for measuring Vt variance based on latch-based comparators. VTS 2017: 1-6 - 2014
- [j5]Kai-Chiang Wu, Ing-Chao Lin, Yao-Te Wang, Shuen-Shiang Yang:
BTI-Aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(10): 1591-1595 (2014) - [j4]Kai-Chiang Wu, Diana Marculescu:
Power-Planning-Aware Soft Error Hardening via Selective Voltage Assignment. IEEE Trans. Very Large Scale Integr. Syst. 22(1): 136-145 (2014) - [j3]Ing-Chao Lin, Kuan-Hui Li, Chia-Hao Lin, Kai-Chiang Wu:
NBTI and Leakage Reduction Using ILP-Based Approach. IEEE Trans. Very Large Scale Integr. Syst. 22(9): 2034-2038 (2014) - 2013
- [j2]Kai-Chiang Wu, Diana Marculescu:
A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 367-379 (2013) - 2012
- [c10]Kai-Chiang Wu, Ming-Chao Lee, Diana Marculescu, Shih-Chieh Chang:
Mitigating lifetime underestimation: A system-level approach considering temperature variations and correlations between failure mechanisms. DATE 2012: 1269-1274 - 2011
- [c9]Kai-Chiang Wu, Diana Marculescu:
Aging-aware timing analysis and optimization considering path sensitization. DATE 2011: 1572-1577 - [c8]Kai-Chiang Wu, Diana Marculescu, Ming-Chao Lee, Shih-Chieh Chang:
Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits. ISLPED 2011: 139-144 - 2010
- [c7]Kai-Chiang Wu, Diana Marculescu:
Clock skew scheduling for soft-error-tolerant sequential circuits. DATE 2010: 717-722
2000 – 2009
- 2009
- [c6]Kai-Chiang Wu, Diana Marculescu:
Joint logic restructuring and pin reordering against NBTI-induced performance degradation. DATE 2009: 75-80 - 2008
- [c5]Kai-Chiang Wu, Diana Marculescu:
Soft error rate reduction using redundancy addition and removal. ASP-DAC 2008: 559-564 - [c4]Natasa Miskov-Zivanov, Kai-Chiang Wu, Diana Marculescu:
Process variability-aware transient fault modeling and analysis. ICCAD 2008: 685-690 - [c3]Kai-Chiang Wu, Diana Marculescu:
Power-aware soft error hardening via selective voltage scaling. ICCD 2008: 301-306 - 2007
- [j1]Shyh-Leh Chen, Kai-Chiang Wu:
Contouring Control of Smooth Paths for Multiaxis Motion Systems Based on Equivalent Errors. IEEE Trans. Control. Syst. Technol. 15(6): 1151-1158 (2007) - 2006
- [c2]Kai-Chiang Wu, Cheng-Tao Hsieh, Shih-Chieh Chang:
Delay variation tolerance for domino circuits. ASP-DAC 2006: 354-359 - 2004
- [c1]Shih-Chieh Chang, Cheng-Tao Hsieh, Kai-Chiang Wu:
Re-synthesis for delay variation tolerance. DAC 2004: 814-819
Coauthor Index
aka: Mango C.-T. Chao
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last updated on 2024-11-25 22:49 CET by the dblp team
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