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"A Low-Power 2-Dimensional Bypassing Multiplier Using 0.35 um CMOS Technology."
Chua-Chin Wang, Gang-Neng Sung (2006)
- Chua-Chin Wang, Gang-Neng Sung:
A Low-Power 2-Dimensional Bypassing Multiplier Using 0.35 um CMOS Technology. ISVLSI 2006: 405-410
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