"Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism."

Saket Srivastava, Aissa Melouki, Bashir M. Al-Hashimi (2009)

> Home

Details and statistics

DOI: 10.1109/NANOARCH.2009.5226354

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

- view
  authority control:
- export record
  dblp key:
  - conf/nanoarch/SrivastavaMA09
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/nanoarch/SrivastavaMA09
Saket Srivastava, Aissa Melouki, Bashir M. Al-Hashimi:
Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. NANOARCH 2009: 43-46

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.