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ORCIDNANOARCH 2009: San Francisco, CA, USA
- 2009 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2009, San Francisco, CA, USA, July 30-31, 2009. IEEE Computer Society 2009, ISBN 978-1-4244-4957-6
- Somnath Paul, Swarup Bhunia
:
Computing with nanoscale memory: Model and architecture. 1-6 - Yiran Chen, Xiaobin Wang:
Compact modeling and corner analysis of spintronic memristor. 7-12 - Patrick Lincoln:
Challenges in scalable fault tolerance. 13-14 - Zahra Mashreghian Arani, Masoud Hashempour, Fabrizio Lombardi:
A coding framework for DNA self-assembly. 15-20 - Aaron Dingler, Michael T. Niemier, Xiaobo Sharon Hu, Michael Garrison, M. Tanvir Alam:
System-level energy and performance projections for nanomagnet-based logic. 21-26 - Nor Zaidi Haron, Said Hamdioui:
Residue-based code for reliable hybrid memories. 27-32 - Eero Lehtonen, Mika Laiho:
Stateful implication logic with memristors. 33-36 - Pritish Narayanan, Csaba Andras Moritz, Kyoung-won Park, Chi On Chui:
Validating cascading of crossbar circuits with an integrated device-circuit exploration. 37-42 - Saket Srivastava, Aissa Melouki, Bashir M. Al-Hashimi:
Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. 43-46 - Inwook Kong, Earl E. Swartzlander Jr., Seong-Wan Kim:
Design of a Goldschmidt iterative divider for quantum-dot cellular automata. 47-50 - Yuan Xie, Soumya Eachempati, Aditya Yanamandra, Vijaykrishnan Narayanan, Mary Jane Irwin:
Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network. 51-56 - Shu Li, Tong Zhang:
Using carbon nanotube in digital memories. 57-60 - Ming Liu, Haigang Yang, Sansiri Tanachutiwat, Wei Wang:
FPGA based on integration of carbon nanorelays and CMOS devices. 61-64 - Ben Kuiper, Sorin Cotofana:
Adaptive Clock Scheduling for pipelined structures. 65-68 - Pierre-Emmanuel Gaillardon, Fabien Clermidy, Ian O'Connor, Junchen Liu:
Interconnection scheme and associated mapping method of reconfigurable cell matrices based on nanoscale devices. 69-74 - Yehua Su, Wenjing Rao:
Runtime analysis for defect-tolerant logic mapping on nanoscale crossbar architectures. 75-78 - Navid Farazmand, Mehdi Baradaran Tahoori:
Online detection of multiple faults in crossbar nano-architectures using dual rail implementations. 79-82
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