"An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay ..."

Kwanyeob Chae et al. (2019)

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DOI: 10.23919/VLSIC.2019.8777959

access: closed

type: Conference or Workshop Paper

metadata version: 2025-09-06

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Kwanyeob Chae, JongRyun Choi, Hyungkwon Lee, Jinho Choi, Shinyoung Yi, Yoonjee Nam, Sangyun Hwang, Joohyung Lee, Won Lee, Kihwan Seong, Joohee Shin, Soo-Min Lee, Seokkyun Ko, Jihun Oh, Billy Koo, Sanghune Park, Jongshin Shin, Hyungjong Ko:
An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme. VLSI Circuits 2019: 96-

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