"Deterministic Low-Latency Data Transfer across Non-Integral Ratio Clock ..."

Suresh Balasubramanian et al. (2006)

> Home

Details and statistics

DOI: 10.1109/VLSID.2006.71

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/vlsid/BalasubramanianNFG06
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsid/BalasubramanianNFG06
Suresh Balasubramanian, Narayanan Natarajan, Olivier Franza, Chris Gianos:
Deterministic Low-Latency Data Transfer across Non-Integral Ratio Clock Domains. VLSI Design 2006: 781-785

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.