default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID19th VLSI Design 2006: Hyderabad, India
- 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India. IEEE Computer Society 2006, ISBN 0-7695-2502-4
Introduction
- Message from the General Chairs.
- Message from the Program Chairs.
- Message from the Organizing Chair.
- Conference Committee.
- Program Committee.
- Organizing Committee.
- VLSI Design 2005 Conference Awards.
- VLSI Design 2006 Conference Awards.
- Reviewers.
- VLSI Design Conference History.
- Embedded Systems Design Conference History.
- Call for Participation: VLSI Design 2007.
- Call for Participation: 10th IEEE VLSI Design & Test Symposium.
Tutorials
- A. V. S. S. Prasad, Jacob Mathews, Nagi Naganathan:
Low-Power Design Strategies for Mobile Computing. 3-4 - Ruchir Puri, Tanay Karnik, Rajiv V. Joshi:
Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies. 5-7 - Shiv Tasker, Rishiyur S. Nikhil:
Beyond RTL: Advanced Digital System Design. 8-9 - Shanthi Pavan, Prakash Easwaran, C. Srinivasan:
System Aspects of Analog to Digital Converter Designs. 10 - N. S. Nagaraj:
Interconnect Process Variations: Theory and Practice. 11 - Goutam Debnath, Paul J. Thadikaran:
Design Challenges for High Performance Nano-Technology. 12-13 - David Abercrombie, Bernd Koenemann, Nagesh Tamarapalli, Srikanth Venkataraman:
DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product Yield. 14 - R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopal, N. Guruprasad, K. Subbarangaiah, Taher Abbasi, D. V. R. Murthy, P. Krishna Prasad, D. R. Gude:
A Comprehensive SoC Design Methodology for Nanometer Design Challenges. 15-17 - Anmol Mathur, Masahiro Fujita, M. Balakrishnan, Raj S. Mitra:
Sequential Equivalence Checking. 18-19 - Parimal Patel:
Embedded Systems Design Using FPGA. 20 - Robert C. Lacovara, Dhadesugoor R. Vaman:
Design of Embedded Systems with Novel Applications. 21-22
Inaugural Keynote Address
- David E. Orton:
Small, Smart, Intelligent and Interactive Handheld Devices. 25
Keynotes
- Richard Miller:
We Want It All, and We Want It Now! 29 - Matthew Rhodes:
Keynote Address. 30 - Henry Potts:
IC/FPGA-Package-PCB Design Collaboration. 31
Banquet Speeches
- Jackson Hu:
The Technological and Geographical Migration of the Semiconductor Industry. 35 - Richard Sevcik:
Future FPGA Technologies, in Partnership with Universities. 36
Plenary Sessions
- Arvind:
UNUM: A Tinker-Toy Approach to Building Multicore PowerPC Microarchitectures. 39 - Mahesh Mehendale:
SoC - The Road Ahead. 40 - Andreas Kuehlmann:
Integrated Design Flows - A Battered EDA Slogan or True Challenge for Tool Development and Algorithmic Research. 41
Session 1A: Analog and Mixed-Signal Design I
- K. Narasimhulu, V. Ramgopal Rao
:
Embedded Tutorial: Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS Technologies. 45-50 - M. S. Bhat, S. Rekha, H. S. Jamadagni:
Extrinsic Analog Synthesis Using Piecewise Linear Current-Mode Circuits. 51-56 - Prabir K. Saha, Ashudeb Dutta, Amit Patra, T. K. Bhattacharyya:
Design of a 1 V Low Power 900 MHz QVCO. 57-62 - Gaurav Raja, Basabi Bhaumik:
16-Bit Segmented Type Current Steering DAC for Video Applications. 63-68 - Subhadeep Banik, Daibashish Gangopadhyay, T. K. Bhattacharyya:
A Low Power 1.8 V 4-Bit 400-MHz Flash ADC in 0.18µ Digital CMOS. 69-74 - Koushik De, Santiram Kal:
A Low Power 6-Bit A/D Converter Achieving 10-Bit Resolution for MEMS Sensor Interface Using Time-Interleaved Delta Modulation. 75-80
Session 1B: VLSI Technology I
- Saraju P. Mohanty, Elias Kougianos:
Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits. 83-88 - Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka, Robert K. Montoye, Richard B. Brown:
Gate-Induced Barrier Field Effect Transistor (GBFET) - A New Thin Film Transistor for Active Matrix Liquid Crystal Display Systems. 89-93 - Thara Rejimon, Sanjukta Bhanja:
Wide Limited Switch Dynamic Logic Circuit Implementations. 94-99 - Mohammad Gh. Mohammad, Laila Terkawi, Muna Albasman:
A Stimulus-Free Probabilistic Model for Single-Event-Upset Sensitivity. 100-107 - M. Jagadesh Kumar, Ali A. Orouji:
Phase Change Memory Faults. 108-112
Session 1C: Interconnect Design I
- Peter Caputa, Christer Svensson:
A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency. 117-122 - Min Tang, Jun-Fa Mao:
Optimization of Global Interconnects in High Performance VLSI Circuits. 123-128 - Shabbir H. Batterywala, Rohit Ananthakrishna, Yansheng Luo, Alex Gyure:
A Statistical Method for Fast and Accurate Capacitance Extraction in the Presence of Floating Dummy Fills. 129-134 - Rohit Ananthakrishna, Shabbir H. Batterywala:
MoM - A Process Variation Aware Statistical Capacitance Extractor. 135-140 - Amitava Bhaduri, Ranga Vemuri:
Parasitic Aware Routing Methodology Based on Higher Order RLCK Moment Metrics. 141-146 - Jin-Tai Yan, Chia-Fang Lee, Yen-Hsiang Chen:
Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing. 147-152
Session 1D: Test and Diagnosis
- Tathagato Rai Dastidar, Partha Ray:
A New Device Level Digital Simulator for Simulation and Functional Verification of Large Semiconductor Memories. 155-160 - Hari Vijay Venkatanarayanan, Michael L. Bushnell:
An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip. 161-168 - Dong Hyun Baik, Kewal K. Saluja:
Test Cost Reduction Using Partitioned Grid Random Access Scan. 169-174 - Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya:
An Efficient Scan Tree Design for Compact Test Pattern Set. 175-180 - Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang:
On Methods to Improve Location Based Logic Diagnosis. 181-187 - Palkesh Jain, D. Vinay Kumar, J. M. Vasi, Mahesh B. Patil:
Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits. 188-193
Session 2A: Communications Module Architecture
- V. Ramakrishnan, Poras T. Balsara:
A Wide-Range, High-Resolution, Compact CMOS, Time to Digital Converter. 197-202 - Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra:
Programmable LDPC Decoder Based on the Bubble-Sort Algorithm. 203-208 - Simon Hollis, Simon W. Moore:
An Asynchronous Interconnect Architecture for Device Security Enhancement. 209-215 - Tong Zhou, Mingyan Yu, Yizheng Ye:
A Pipelined Switched-Current Chaotic System for the High-Speed Truly Random Number Generation in Crypto Processor. 216-221
Session 2B: Formal Verification
- Qiang Qiang, Daniel G. Saab, Jacob A. Abraham:
Checking Nested Properties Using Bounded Model Checking and Sequential ATPG. 225-230 - Praveen Tiwari, Saptarshi Biswas, Raj S. Mitra:
Apriori Formal Coverage Analysis for Protocol Properties. 231-236 - Rolf Drechsler, Görschwin Fey, Sebastian Kinder:
An Integrated Approach for Combining BDD and SAT Provers. 237-242 - Aman Kokrady, Theo J. Powell, S. Ramakrishnan:
Reducing Design Verification Cycle Time through Testbench Redundancy. 243-248
Session 2C: VLSI Architecture and FPGAs
- Xin Jia, Ranga Vemuri:
CAD Tools for a Globally Asynchronous Locally Synchronous FPGA Architecture. 251-256 - Yan Feng, Dinesh P. Mehta:
Heterogeneous Floorplanning for FPGAs. 257-262 - Mark P. Tennant, Ahmet T. Erdogan, Tughrul Arslan, John S. Thompson:
A Novel Architecture Using the Decorrelating Transform for Low Power Adaptive Filters. 263-268
Session 2D: Crosstalk Analysis
- Amit Kumar, Noriyuki Miura, Muhammad Muqsith, Tadahiro Kuroda:
Active Crosstalk Cancel for High-Density Inductive Inter-chip Wireless Communication. 271-276 - K. A. Rajagopal, R. Sivakumar, N. V. Arvind, C. Sreeram, Vish Visvanathan, Shailendra Dhuri, Roopesh Chander, Patrick Fortner, Subra Sripada, Qiuyang Wu:
A Comprehensive Solution for True Hierarchical Timing and Crosstalk Delay Signoff. 277-282 - Narender Hanchate, Nagarajan Ranganathan:
A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise. 283-290
Session 3A: High-Level and Logic Synthesis
- Samik Das, P. P. Chakrabarti, Pallab Dasgupta:
Instruction-Set-Extension Exploration Using Decomposable Heuristic Search. 293-298 - Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha:
Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors. 299-304 - Biman Chakraborty, Ting Chen, Tulika Mitra, Abhik Roychoudhury:
Handling Constraints in Multi-Objective GA for Embedded System Design. 305-310 - Ahsan Raja Chowdhury, Rumana Nazmul, Hafiz Md. Hasan Babu:
A New Approach to Synthesize Multiple-Output Functions Using Reversible Programmable Logic Array. 311-316 - Rui Zhang, Niraj K. Jha:
State Encoding of Finite-State Machines Targeting Threshold and Majority Logic Based Implementations with Application to Nanotechnologies. 317-322 - Jayashree Sridharan, Tom Chen:
Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing Analysis. 323-328
Session 3B: Distribution and Noise Modeling
- R. G. Raghavendra, Pradip Mandal:
An On-Chip Voltage Regulator with Improved Load Regulation and Light Load Power Efficiency. 331-336 - Puneet Gupta, Andrew B. Kahng:
Efficient Design and Analysis of Robust Power Distribution Meshes. 337-342 - Debasis Mitra, Subhasis Bhattacharjee, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sujit T. Zachariah, Sandip Kundu:
Test Pattern Generation for Power Supply Droop Faults. 343-348 - Baohua Wang, Pinaki Mazumder:
Bounding Supply Noise Induced Path Delay Variation Using a Relaxation Approach. 349-354 - Subodh M. Reddy, Rajeev Murgai:
Accurate Substrate Noise Analysis Based on Library Module Characterization. 355-362 - Venkat Rao Vallapenani, Ravi Shankar Chevuri, Bingxiong Xu, Lun Ye, Kanad Chakraborty:
Efficient Techniques for Noise Characterization of Sequential Cells and Macros. 363-368
Session 3C: Multimedia and Arithmetic Architecture
- Soumyajit Dey, Susmit Biswas, Arijit Mukhopadhyay, Anupam Basu:
An Approach to Architectural Enhancement for Embedded Speech Applications. 371-376 - Jun Chen, Rong Luo, Huazhong Yang, Hui Wang:
A Low Power ROM-Less Direct Digital Frequency Synthesizer with Preset Value Pipelined Accumulator. 377-380 - Rama Sangireddy, Prabhu Rajamani, Shwetha Gaddam:
Performance Optimization with Scalable Reconfigurable Computing Systems. 381-386 - Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas:
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format. 387-392 - Venkataraman Mahalingam, N. Ranganathan:
An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition. 393-398 - Higinio Mora Mora, Jerónimo Mora Pascual, José-Luis Sánchez-Romero, Francisco Antonio Pujol López:
Partial Product Reduction Based on Look-Up Tables. 399-404
Session 3D: Test Algorithms
- Suresh Kumar Devanathan, Michael L. Bushnell:
Sequential Spectral ATPG Using the Wavelet Transform and Compaction. 407-412 - Shweta Chary, Michael L. Bushnell:
Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. 413-418 - Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic. 419-424 - Kalyana R. Kantipudi:
On the Size and Generation of Minimal N-Detection Tests. 425-430 - Loganathan Lingappan, Niraj K. Jha:
Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults. 431-436 - Achintya Halder, Abhijit Chatterjee:
Low-Cost Production Testing of Wireless Transmitters. 437-442
Panel: VC Forum
Special Session: Emerging Technologies
- Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici:
Double-Gate SOI Devices for Low-Power and High-Performance Applications. 445-452 - Ali Javey, Hongjie Dai:
Carbon Nanotube Electronics. 453-458
Session 4A: Synthesis and Partitioning
- Ivan Radojevic, Zoran A. Salcic, Partha S. Roop:
Design of Heterogeneous Embedded Systems Using DFCharts Model of Computation. 461-464 - David Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee:
Dynamic Template Generation for Resource Sharing in Control and Data Flow Graphs. 465-468 - Anirban Lahiri, Saurabh Agarwal, Anupam Basu, Bhargab B. Bhattacharya:
Recovery-Based Real-Time Static Scheduling for Battery Life Optimization. 469-472 - Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors. 473-476 - Viswanath Sairaman, Nagarajan Ranganathan, Neeta S. Singh:
An Automatic Code Generation Tool for Partitioned Software in Distributed Systems. 477-480 - Naga M. Kosaraju, Murali R. Varanasi, Saraju P. Mohanty:
A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm. 481-484
Session 4B: Memory and Logic Design
- Motoi Ichihashi, Haruki Toda:
Performance Measurement and Improvement of Asymmetric Three-Tr. Cell (ATC) DRAM toward 0.3V Memory Array Operation. 487-490 - Ashok Narasimhan, Bhooma Srinivasaraghavan, Ramalingam Sridhar:
A Low-Power Asymmetric Source Driver Level Converter Based Current-Mode Signaling Scheme for Global Interconnects. 491-494 - Sanjeev K. Jain, Pankaj Agarwal:
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology. 495-498 - R. Rajaraman, Jungsub Kim, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
SEAT-LA: A Soft Error Analysis Tool for Combinational Logic. 499-502 - Siva Embanath, Ramakrishnan Venkata:
Exceptional ASIC: Through Automatic Timing Exception Generation (ATEG). 503-506 - Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti:
An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs. 507-510
Session 4C: Communications and Multimedia Architecture I
- Alok Kumar Pani, Ratnam V. Raja Kumar:
Optimized VLIW Architecture for Non-zero IF QAM-Modem Implementations. 513-516 - Kavish Seth, K. N. Viswajith, S. Srinivasan, V. Kamakoti:
Ultra Folded High-Speed Architectures for Reed-Solomon Decoders. 517-520 - Mian Dong, Chun Zhang, Songping Mai, Zhihua Wang, Dongmei Li:
A Wideband Frequency-Shift Keying Demodulator for Wireless Neural Stimulation Microsystems. 521-524 - Simon Ogg, Bashir M. Al-Hashimi:
Improved Data Compression for Serial Interconnected Network on Chip through Unused Significant Bit Removal. 525-529 - Anand Gautam, A. Geeta Madhuri, Priya Khandelwal, K. Pratyush Aditya, Meghana Desai, Padma N. Krishna, Malvika Dutt, Reeti Bhatia:
Novel Architecture of EBC for JPEG2000. 530-533 - J. Bhattacharyya, P. Mandal, R. Banerjee, Swapna Banerjee:
Real Time Dynamic Receive Apodization for an Ultrasound Imaging System. 534-537
Session 4D: VLSI Technology II
- Rajendra M. Patrikar, Olivier Peyran:
Design Planning for Uniform Thermal Distribution. 541-544 - Subhashis Majumder, Bhargab B. Bhattacharya:
Solving Thermal Problems of Hot Chips Using Voronoi Diagrams. 545-548 - Deepanjan Datta, Samiran Ganguly:
Design of Multi-bit SET Adder and Its Fault Simulation. 549-552 - Mengmeng Ding, Ranga Vemuri:
Efficient Analog Performance Macromodeling via Sequential Design Space Decomposition. 553-556 - Qadeer Ahmad Khan, Sanjay Kumar Wadhwa, Kulbhushan Misri:
A Single Supply Level Shifter for Multi-Voltage Systems. 557-560
Session 5A: Analog and Mixed-Signal Design II
- Zhiyuan Li, Mingyan Yu, Jianguo Ma:
A Rail-to-Rail I/O Operational Amplifier with 0.5% gm Fluctuation Using Double P-channel Differential Input Pairs. 563-568 - Srikanth Sundaram, Praveen Elakkumanan, Ramalingam Sridhar:
High Speed Robust Current Sense Amplifier for Nanoscale Memories: - A Winner Take All Approach. 569-574 - Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran:
ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective. 575-580 - Qadeer Ahmad Khan, G. K. Siddhartha, Divya Tripathi, Sanjay Kumar Wadhwa, Kulbhushan Misri:
Techniques for On-Chip Process Voltage and Temperature Detection and Compensation. 581-586 - Debashis Dutta, Ritesh Ujjwal, Swapna Banerjee:
Design of Low-Voltage Low-Power Continuous-Time Filter for Hearing Aid Application Using CMOS Current Conveyor Based Translinear Loop. 587-592 - Sanjoy Kumar Dey, Swapna Banerjee:
An 8-Bit, 3.8GHz Dynamic BiCMOS Comparator for High-Performance ADC. 593-598
Session 5B: Low Power/RF Design
- K. Sadeghi, M. Emadi, Farzan Farbiz:
Using Level Restoring Method for Dual Supply Voltage. 601-605 - Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak:
Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. 606-612 - Koushik Maharatna, Alfonso Troya, Milos Krstic, Eckhard Grass:
On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder. 613-618 - Sushanta K. Mandal, Arijit De, Amit Patra, Shamik Sural:
A Wide-Band Lumped Element Compact CAD Model of Si-Based Planar Spiral Inductor for RFIC Design. 619-624 - G. Girishankar, Shitanshu Tiwari:
Generating Scalable Polynomial Models: Key to Low Power High Performance Designs. 625-630 - Sanjay Kumar Wadhwa, G. K. Siddhartha, Anand Gaurav:
Zero Steady State Current Power on Reset Circuit with Brown-Out Detector. 631-636
Session 5C: Embedded Systems
- Haris Lekatsas, Jörg Henkel, Venkata Jakkula, Srimat T. Chakradhar:
Using Shiftable Content Addressable Memories to Double Memory Capacity on Embedded Systems. 639-644 - Viswanathan Lakshmi Prabha, Elwin Chandra Monie:
Reinforcement Temporal Difference Learning Scheme for Dynamic Energy Management in Embedded Systems. 645-650 - Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi:
Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core. 651-656 - Thomas D. Richardson, Chrysostomos Nicopoulos, Dongkook Park, Narayanan Vijaykrishnan, Yuan Xie, Chita R. Das, Vijay Degalahal:
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks. 657-664
Session 5D: Design Tools
- Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla:
Circuit Compatible Macromodeling of High-Speed VLSI Modules Characterized by Scattering Parameters. 667-671 - Gurpreet Shinh, Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Ihsan Erdin:
Efficient and Accurate EMC Analysis of High-Frequency VLSI Subnetworks. 672-676 - Arnab Sarkar, P. P. Chakrabarti, Rajeev Kumar:
Frame Based Fair Multiprocessor Scheduler: A Fast Fair Algorithm for Real-Time Embedded Systems. 677-682 - Sandip Aine, P. P. Chakrabarti, Rajeev Kumar:
Improving the Performance of CAD Optimization Algorithms Using On-Line Meta-Level Control. 683-688 - Ritochit Chakraborty, Mukesh Ranjan, Ranga Vemuri:
Symbolic Time-Domain Behavioral and Performance Modeling of Linear Analog Circuits Using an Efficient Symbolic Newton-Iteration Algorithm for Pole Extraction. 689-694 - Gaurav Trivedi, Madhav P. Desai, H. Narayanan:
Fast DC Analysis and Its Application to Combinatorial Optimization Problems. 695-700
Special Session : Emerging Technologies
- Mircea R. Stan, Garrett S. Rose, Matthew M. Ziegler:
Hybrid CMOS/Molecular Electronic Circuits. 703-708 - Vivek Subramanian, Paul C. Chang, Daniel C. Huang, Josephine B. Lee, Steven E. Molesa, David R. Redinger, Steven K. Volkman:
All-Printed RFID Tags: Materials, Devices, and Circuit Implications. 709-714
Session 6A: Analog Design/MEMS
- Roopak Suri, C. M. Markan:
Threshold Trimming Based Design of a CMOS Programmable Operational Amplifier. 717-720 - T. K. Bhattacharyya, Shreyas Sen, Debashis Mandal, S. K. Lahiri:
Development of a Wireless Integrated Toxic and Explosive MEMS Based Gas Sensor. 721-724 - Evangelos F. Stefatos, Tughrul Arslan, Didier Keymeulen, Ian Ferguson:
Custom Reconfigurable Architecture for Autonomous Fault-Recovery of MEMS Vibratory Sensor Electronics. 725-728 - Soumendu Bhattacharya, Vishwanath Natarajan, Abhijit Chatterjee, Sankar Nair:
Efficient DNA Sensing with Fabricated Silicon Nanopores: Diagnosis Methodology and Algorithms. 729-733 - Zahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan:
Area and Power Efficient VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System. 734-737 - Supriya S. Shanbhag:
CMOS Integrated Circuit for Sensing Applications. 738-741
Session 6B: Low Power Design I
- V. S. Kanchana Bhaaskaran, S. Salivahanan, D. S. Emmanuel:
Semi-Custom Design of Adiabatic Adder Circuits. 745-748 - Abdelhalim Alsharqawi, Abdel Ejnioui:
Clockless Pipelining for Coarse Grain Datapaths. 749-753 - Rajan Konar, Rajarshee P. Bharadwaj, Dinesh Bhatia, Poras T. Balsara:
Exploring Logic Block Granularity in Leakage Tolerant FPGA. 754-757 - Koushik K. Das, Shih-Hsien Lo, Ching-Te Chuang:
High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header. 758-761 - Yen-Jen Chang:
An Alternative Real-Time Filter Scheme to Block Buffering. 762-765 - Aswath Oruganti, Nagarajan Ranganathan:
Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation. 766-769
Session 6C: Interconnect Design II
- Ajay Joshi, Vinita V. Deodhar, Jeffrey A. Davis:
Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing. 773-776 - Alkan Cengiz, Tom W. Chen:
A Progressive Two-Stage Global Routing for Macro-Cell Based Designs. 777-780 - Suresh Balasubramanian, Narayanan Natarajan, Olivier Franza, Chris Gianos:
Deterministic Low-Latency Data Transfer across Non-Integral Ratio Clock Domains. 781-785 - Usha Narasimha, Anthony M. Hill, N. S. Nagaraj:
SmartExtract: Accurate Capacitance Extraction for SOC Designs. 786-789 - Parthasarathi Dasgupta, Prashant Yadava:
Linear Required-Arrival-Time Trees and their Construction. 790-793 - Snehashis Roy, Sukumar Jairam, H. Udayakumar:
A Methodology for Switching Activity Based IO Powerpad Optimisation. 794-797
Session 6D: Test and Design-for-Testability
- Omar I. Khan, Michael L. Bushnell:
Aliasing Analysis of Spectral Statistical Response Compaction Techniques. 801-806 - Priya Iyer, Shailendra Jain, Bryan Casper, Jason Howard:
Testing High-Speed IO Links Using On-Die Circuitry. 807-810 - Kedarnath J. Balakrishnan, Seongmoon Wang, Srimat T. Chakradhar:
PIDISC: Pattern Independent Design Independent Seed Compression Technique. 811-817 - Shweta Chary, Michael L. Bushnell:
Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. 818-823 - Ramesh C. Tekumalla:
An On-Chip Diagnosis Methodology for Embedded Cores with Replaceable Modules. 824-827 - Irith Pomeranz, Sudhakar M. Reddy:
The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for Transition Faults. 828-831
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-09 23:23 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
