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ORCID"Reducing Design Verification Cycle Time through Testbench Redundancy."
Aman Kokrady, Theo J. Powell, S. Ramakrishnan (2006)
- Aman Kokrady, Theo J. Powell, S. Ramakrishnan:
Reducing Design Verification Cycle Time through Testbench Redundancy. VLSI Design 2006: 243-248
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