"A 1.1pJ/b/Lane, 1.8Tb/s Chiplet Over XSR-MCM Channels Using 113Gb/s PAM-4 ..."

Gautam R. Gangasani et al. (2024)

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DOI: 10.1109/VLSITECHNOLOGYANDCIR46783.2024.10631427

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type: Conference or Workshop Paper

metadata version: 2024-10-17

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Gautam R. Gangasani, A. Mostafa, A. Singh, Daniel W. Storaska, D. Prabakaran, K. Mohammad, Matthew Baecher, M. Shannon, Michael Sorna, Michael Wielgos, P. Jenkins, P. B. Ramakrishna, U. K. Shukla:
A 1.1pJ/b/Lane, 1.8Tb/s Chiplet Over XSR-MCM Channels Using 113Gb/s PAM-4 Transceiver with Signal Equalization and Envelope Adaptation Using TX-FFE in 5nm CMOS. VLSI Technology and Circuits 2024: 1-2

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